coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: fafa0d9 crossgcc/buildgcc: Remove unneeded 'break' statements
by Paul Menzel 29 May '13

29 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3330 -gerrit commit fafa0d90b9b61b852c47110d5ae0788cabb15834 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Tue May 28 16:33:15 2013 -0600 crossgcc/buildgcc: Remove unneeded 'break' statements Bash case statements are terminated with ';;'. Unlike C, bash case statements will not continue to the next case. No 'break' is needed. Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036 Signed-off-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> --- util/crossgcc/buildgcc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c436f8e..1d8e54c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -215,16 +215,16 @@ while true ; do -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; - --) shift; break;; + --) shift;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; - *) break;; + *) ;; esac done case "$TARGETARCH" in - armv7a-eabi) break;; - i386-elf) break;; - i386-mingw32) break;; + armv7a-eabi) ;; + i386-elf) ;; + i386-mingw32) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=armv7a-eabi;; *) printf "Invalid architecture\n\n"; myhelp; exit 1;;

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Patch set updated for coreboot: a11374e crosgcc/buildgcc: Remove unneeded 'break' statements
by Paul Menzel 29 May '13

29 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3330 -gerrit commit a11374e0ec2e15bb775b5674bdf3ea14db0b25a0 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Tue May 28 16:33:15 2013 -0600 crosgcc/buildgcc: Remove unneeded 'break' statements Bash case statements are terminated with ';;'. Unlike C, bash case statements will not continue to the next case. No 'break' is needed. Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036 Signed-off-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> --- util/crossgcc/buildgcc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c436f8e..1d8e54c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -215,16 +215,16 @@ while true ; do -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; - --) shift; break;; + --) shift;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; - *) break;; + *) ;; esac done case "$TARGETARCH" in - armv7a-eabi) break;; - i386-elf) break;; - i386-mingw32) break;; + armv7a-eabi) ;; + i386-elf) ;; + i386-mingw32) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=armv7a-eabi;; *) printf "Invalid architecture\n\n"; myhelp; exit 1;;

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New patch to review for coreboot: 040f83c Remove unneeded 'break' statements
by David Hubbard 29 May '13

29 May '13

David Hubbard (david.c.hubbard+coreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3330 -gerrit commit 040f83c64e7c982f38fdf1c8333271ba34066603 Author: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Date: Tue May 28 16:33:15 2013 -0600 Remove unneeded 'break' statements Bash case statements are terminated with ;; Unlike C, bash case statements will not continue to the next case. No 'break' is needed. Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036 Signed-off-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> --- util/crossgcc/buildgcc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c436f8e..1d8e54c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -215,16 +215,16 @@ while true ; do -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; - --) shift; break;; + --) shift;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; - *) break;; + *) ;; esac done case "$TARGETARCH" in - armv7a-eabi) break;; - i386-elf) break;; - i386-mingw32) break;; + armv7a-eabi) ;; + i386-elf) ;; + i386-mingw32) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=armv7a-eabi;; *) printf "Invalid architecture\n\n"; myhelp; exit 1;;

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New patch to review for coreboot: 0558132 beaglebone: Force on every other user LED to show that Coreboot is running.
by Gabe Black 28 May '13

28 May '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3329 -gerrit commit 0558132747bca247c7f0c1e920e8b8d6b95d167b Author: Gabe Black <gabeblack(a)google.com> Date: Mon May 27 22:38:59 2013 +0200 beaglebone: Force on every other user LED to show that Coreboot is running. Until we get serial working, this is a good way to show that Coreboot is running. It can be removed once we have better methods. Change-Id: I62d25e52aa88a97aba4c959538d680b67a0bbbb2 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 77e382d..fbe73ea 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <types.h> #include <uart.h> #include <console/console.h> @@ -24,6 +25,19 @@ void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + /* Enable the GPIO module */ + writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); + + /* Disable interrupts from these GPIOs */ + setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21); + + /* Enable output */ + clrbits_le32((uint32_t *)(0x4804c000 + 0x134), 0xf << 21); + + /* Set every other light */ + clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); + setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + /* Start monotonic timer */ //rtc_start();

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New patch to review for coreboot: de16459 beaglebone: Reduce the size of the "ROM" from 128K to 64K
by Gabe Black 28 May '13

28 May '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3328 -gerrit commit de164593b5c8c5896e44fe5455ecb34a0e05bdad Author: Gabe Black <gabeblack(a)google.com> Date: Mon May 27 22:18:22 2013 +0200 beaglebone: Reduce the size of the "ROM" from 128K to 64K The RAM interal to the SOC isn't quite 128K in size, and has some things in it that would be best not to trample. The current model is to load the entire image into this memory and then to seperately load the RAM stage into the system memory when that gets set up. Change-Id: I89dc658fb1d14457a657ce3ecd2fd4d6acfb893f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 97fdf48..9260a2f 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_TI_AM335X select HAVE_UART_MEMORY_MAPPED # FIXME: This should be much smaller - select BOARD_ROMSIZE_KB_128 + select BOARD_ROMSIZE_KB_64 config MAINBOARD_DIR string

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New patch to review for coreboot: ce0a750 am335x: Clean up/fix some settings in the am335x Kconfig.
by Gabe Black 28 May '13

28 May '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3327 -gerrit commit ce0a7502349f6f5c773f6f84197b006bd2317a0b Author: Gabe Black <gabeblack(a)google.com> Date: Mon May 27 22:16:13 2013 +0200 am335x: Clean up/fix some settings in the am335x Kconfig. Some settings in the am335x Kconfig weren't actually used for anything, some where place holders, and some where left over from another CPU. Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Kconfig | 39 ++++----------------------------------- 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index c4ef8f1..472fbe7 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,25 +6,9 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -# Example SRAM/iRAM map for Exynos5250 platform: -# -# 0x0202_3400: bootblock, assume up to 32KB in size -# 0x0203_0000: romstage, assume up to 128KB in size. -# 0x0207_8000: stack pointer - -# FIXME: find out where romboot places ml0/coreboot config BOOTBLOCK_BASE hex - default 0xdeadbeef - -#config ROMSTAGE_BASE -# hex -# default 0x02030000 -# -# FIXME: this is bullshit. -config ROMSTAGE_SIZE - hex - default 0xa000 + default 0x402f0400 # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -33,11 +17,11 @@ config ROMSTAGE_SIZE # consecutive memory locations ending just below SP config STACK_TOP hex - default 0x02078000 + default 0x4030ce00 config STACK_BOTTOM hex - default 0x02077000 + default 0x4030be00 config STACK_SIZE hex @@ -46,7 +30,7 @@ config STACK_SIZE config CBFS_ROM_OFFSET # Calculated by BL1 + max bootblock size. hex "offset of CBFS data in ROM" - default 0x0A000 + default 0x2800 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. @@ -54,21 +38,6 @@ config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" default 0x40 -## TODO We may probably move this to board-specific implementation files instead -## of KConfig values. -#config CBFS_CACHE_ADDRESS -# hex "memory address to put CBFS cache data" -# default 0x02060000 -# -#config CBFS_CACHE_SIZE -# hex "size of CBFS cache data" -# default 0x000017000 - -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x40000000

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New patch to review for coreboot: 6358465 AMD Geode LX: Add AES PCI device 0:1.2 to `devicetree.cb`
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3326 -gerrit commit 6358465ec24f937ec415e0f53400ccc533640694 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 28 20:59:50 2013 +0200 AMD Geode LX: Add AES PCI device 0:1.2 to `devicetree.cb` The AMD Geode LX processor features a security block [1], which is exposed as PCI device 0:1.2. Currently some Geode LX boards in the tree mention it in their `devicetree.cb` and others do not. So add device pci 1.2 on end # AES to the boards not having this line to completely describe the devices. No functionality is changed, as coreboot was able to discover the AES security block anyway. 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082] The following command was used to find all Geode LX `devicetree.cb` files. $ find src/mainboard -name devicetree.cb | xargs grep -l 'amd/lx' [1] http://en.wikipedia.org/wiki/AMD_Geode#Geode_LX Change-Id: Id4565c83ac2c0a3f2994535650bb9f642c0feced Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/db800/devicetree.cb | 1 + src/mainboard/amd/norwich/devicetree.cb | 1 + src/mainboard/artecgroup/dbe61/devicetree.cb | 1 + src/mainboard/digitallogic/msm800sev/devicetree.cb | 1 + src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb | 1 + src/mainboard/pcengines/alix1c/devicetree.cb | 1 + src/mainboard/pcengines/alix2d/devicetree.cb | 1 + src/mainboard/traverse/geos/devicetree.cb | 1 + src/mainboard/winent/pl6064/devicetree.cb | 1 + 9 files changed, 9 insertions(+) diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index 3331a12..db78d7c 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 93effaa..0eba4d7 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb index d270f3d..59e3215 100644 --- a/src/mainboard/artecgroup/dbe61/devicetree.cb +++ b/src/mainboard/artecgroup/dbe61/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 839b767..63377ec 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb index a6dba30..b30c169 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb +++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 85e967a..e33d277 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index d8aa3bc..2b51908 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb index 4a2674e..fbf0bb6 100644 --- a/src/mainboard/traverse/geos/devicetree.cb +++ b/src/mainboard/traverse/geos/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index f900f78..4b88479 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power....

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New patch to review for coreboot: f56520f AMD AGESA boards: Reference arrays by variable name and not first element
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3325 -gerrit commit f56520f79e588256ff057c1a872964db5e871659 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 28 20:38:56 2013 +0200 AMD AGESA boards: Reference arrays by variable name and not first element Not yet ready. The former patches can be submitted. Though. Additionally for arrays like `… PortList [] …`, instead of `&PortList[0]` reference them by `PortList` as suggested by Ron G. Minnich [1]. [1] http://review.coreboot.org/#/c/3247/3/src/mainboard/asus/f2a85-m/PlatformGn… Change-Id: Ie6be0e42ec2cfb57a8d2cb2aec497a5c5387d015 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index 50a8db9..e564851 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -109,8 +109,8 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_COMPLEX_DESCRIPTOR Brazos = { DESCRIPTOR_TERMINATE_LIST, 0, - &PortList[0], - &DdiList[0] + PortList, + DdiList }; // GNB PCIe topology Porting @@ -153,8 +153,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, PortList, sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, DdiList, sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;

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Patch set updated for coreboot: 91fc962 AMD Trinity boards: Use `sizeof(var)` to get its size
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3247 -gerrit commit 91fc962d34e16d4118962200ea5da079c2bd5558 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 AMD Trinity boards: Use `sizeof(var)` to get its size Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 20 +++++++++----------- 3 files changed, 27 insertions(+), 33 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index d3d66a3..1925db8 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -183,9 +183,7 @@ OemCustomizeInitEarly ( /* */ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ /* */ - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 3; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -198,30 +196,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 3, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 3837341..ec5d68d 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -182,9 +182,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 3; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -197,30 +195,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 3, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8907c13..fff40a8 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -204,9 +204,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 6; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -219,30 +217,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;

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Patch set updated for coreboot: 6c84286 ASUS F2A85-M: Correct and clean up PCIe config
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3194 -gerrit commit 6c84286e4246d6af1a1b3da10bd5a548dac8c323 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 ASUS F2A85-M: Correct and clean up PCIe config Assign the lanes correctly to the physical slots on the motherboard in `PlatformGnbPcie.c`. • UMI is connected to SB via 4x PCIe bridge 8. • The blue x16 slot is not shared with DDI and is routed through PCIe bridge 2. • The black x8 slot is in fact a x4 slot and uses all 4 GPPs from the CPU. • Assume that DDI is on out-of-PCIe-band lanes. Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 66 ++++------------------ .../asus/f2a85-m/PlatformGnbPcieComplex.h | 40 ------------- 2 files changed, 10 insertions(+), 96 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index fff40a8..8ff64c6 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -72,57 +72,32 @@ */ PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ - { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - -#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif }; +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI + * Untested: HDMI + */ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP { @@ -139,29 +114,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP2 to HDMI1/DP { 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -205,7 +160,6 @@ OemCustomizeInitEarly ( // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly

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coreboot-gerrit May 2013