coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: fa7c7a1 Lenovo X60: Add CMOS defaults.
by Denis Carikli 29 May '13

29 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3335 -gerrit commit fa7c7a19d1fd21c5ee35199541abd6a551bfd583 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed May 29 21:25:05 2013 +0200 Lenovo X60: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback baud_rate = 115200 debug_level = Spew hyper_threading = Enable nmi = Enable boot_devices = '' boot_default = 0x40 cmos_defaults_loaded = Yes lpt = Enable volume = 0xff tft_brightness = 0xbf first_battery = Primary bluetooth = Enable The code for handling the invalid CMOS space in mainboard.c is now useless and so it was removed. Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/cmos.default | 14 ++++++++++++++ src/mainboard/lenovo/x60/mainboard.c | 17 ----------------- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..5ecad2f 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_LENOVO_H8 select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select MMCONF_SUPPORT diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default new file mode 100644 index 0000000..f5e4afa --- /dev/null +++ b/src/mainboard/lenovo/x60/cmos.default @@ -0,0 +1,14 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +boot_default=0x40 +cmos_defaults_loaded=Yes +lpt=Enable +volume=0x3 +tft_brightness=0xf +first_battery=Primary +bluetooth=Enable diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 3cb28ff..032d641 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -54,7 +54,6 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_enable(device_t dev) { device_t dev0, idedev, sdhci_dev; - u8 defaults_loaded = 0; ec_clr_bit(0x03, 2); @@ -92,22 +91,6 @@ static void mainboard_enable(device_t dev) pci_write_config8(sdhci_dev, 0xf9, 0x00); } } - - if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { - printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); - defaults_loaded = 0; - } - - if (!defaults_loaded) { - printk(BIOS_INFO, "Restoring CMOS defaults\n"); - set_option("tft_brightness", &(u8[]){ 0xff }); - set_option("volume", &(u8[]){ 0x03 }); - /* set baudrate to 115200 baud */ - set_option("baud_rate", &(u8[]){ 0x00 }); - /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ - set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); - set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); - } } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: 8cfd56e PC Engines ALIX.1C: Add CMOS defaults.
by Denis Carikli 29 May '13

29 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3323 -gerrit commit 8cfd56ecdcc4b99a8079f8f250a1fd94e35ef1f2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 2 ++ src/mainboard/pcengines/alix1c/cmos.default | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..fab8710 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default new file mode 100644 index 0000000..189c691 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -0,0 +1,11 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0x7f

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Patch set updated for coreboot: 591fe45 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 29 May '13

29 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3324 -gerrit commit 591fe45ac92b9bc1ebbda9746836e543d8412a27 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

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Patch set updated for coreboot: da9dfd4 Provide sane Kconfig default for cmos.default.
by Denis Carikli 29 May '13

29 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3223 -gerrit commit da9dfd48fb99f9908b5849ff71ffb4c3bed0ce24 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue May 28 13:46:12 2013 +0200 Provide sane Kconfig default for cmos.default. Without that fix we have with CONFIG_USE_OPTION_TABLE: OPTION cmos_layout.bin build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c That log was captured with make V=1 but the error also appear with make. This commit was tested on the PC Engines ALIX.1C with the following commit: PC Engines ALIX.1C: Add CMOS defaults. Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..c7b2434 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,6 +81,7 @@ config HAVE_CMOS_DEFAULT config CMOS_DEFAULT_FILE string + default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT config BOOTBLOCK_SOUTHBRIDGE_INIT

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Patch set updated for coreboot: 8d3da30 AMD Geode CS5536: downgrade BIOS_ERR
by Christian Gmeiner 29 May '13

29 May '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3307 -gerrit commit 8d3da30d775842f5c20e7c80f135cb931ab47782 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed May 29 20:30:18 2013 +0000 AMD Geode CS5536: downgrade BIOS_ERR There is no need to use everywhere BIOS_ERR. Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/southbridge/amd/cs5536/cs5536.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index bec0e89..e305594 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -582,7 +582,7 @@ void chipsetinit(void) } /* Flash BAR size Setup */ - printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n", + printk(BIOS_INFO, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); @@ -610,7 +610,7 @@ static void southbridge_init(struct device *dev) * unsigned short gpiobase = MDD_GPIO; */ - printk(BIOS_ERR, "cs5536: %s\n", __func__); + printk(BIOS_INFO, "cs5536: %s\n", __func__); if (!sb) { printk(BIOS_ERR, "CS5536 configuration not found.\n"); @@ -628,7 +628,7 @@ static void southbridge_init(struct device *dev) (sb->enable_gpio_int_route >> 16)); } - printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, + printk(BIOS_DEBUG, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); @@ -665,7 +665,7 @@ static void cs5536_read_resources(device_t dev) static void southbridge_enable(struct device *dev) { - printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev); + printk(BIOS_DEBUG, "cs5536: %s: dev is %p\n", __func__, dev); }

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Patch merged into coreboot/master: 1a71f4c qemu: remove vga hook
by gerrit＠coreboot.org 29 May '13

29 May '13

the following patch was just integrated into master: commit 1a71f4c21f86fe058da9dee3be1d9db5448fe1b7 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed May 29 14:53:03 2013 +0200 qemu: remove vga hook Extra care for the qemu vga should not be needed any more. Since release 0.12 qemu loads the vgabios into the PCI ROM bar, so everything works exactly like it does on real hardware. Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3333 for details. -gerrit

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Patch set updated for coreboot: ecc77db beaglebone: Reduce the size of the "ROM" from 128K to 64K
by Paul Menzel 29 May '13

29 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3328 -gerrit commit ecc77dbe909599373a999574d273726b2b9f98bd Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed May 29 16:42:27 2013 +0200 beaglebone: Reduce the size of the "ROM" from 128K to 64K The RAM internal to the SOC isn't quite 128K in size, and has some things in it that would be best not to trample. The current model is to load the entire image into this memory and then to seperately load the RAM stage into the system memory when that gets set up. Change-Id: I89dc658fb1d14457a657ce3ecd2fd4d6acfb893f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 97fdf48..9260a2f 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_TI_AM335X select HAVE_UART_MEMORY_MAPPED # FIXME: This should be much smaller - select BOARD_ROMSIZE_KB_128 + select BOARD_ROMSIZE_KB_64 config MAINBOARD_DIR string

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New patch to review for coreboot: b27c38c qemu: fix IRQ routing setup
by Gerd Hoffmann 29 May '13

29 May '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3334 -gerrit commit b27c38c53d5a2653caa85d81e5c2979620d5a64d Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed May 29 14:59:36 2013 +0200 qemu: fix IRQ routing setup Do it for all PCI slots, not only 3. Also remove the bogous message, slot 3 may carry any device, not only NICs. Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-x86/mainboard.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index ae92654..4f86e16 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -26,8 +26,7 @@ #include <pc80/keyboard.h> #include <arch/io.h> -/* not sure how these are routed in qemu */ -static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; +static const unsigned char qemu_i440fx_irqs[4] = { 10, 10, 11, 11 }; static void qemu_nb_init(device_t dev) { @@ -44,11 +43,10 @@ static void qemu_nb_init(device_t dev) */ pc_keyboard_init(0); - /* The PIRQ table is not working well for interrupt routing purposes. - * so we'll just set the IRQ directly. - */ - printk(BIOS_INFO, "Setting up ethernet...\n"); - pci_assign_irqs(0, 3, enetIrqs); + /* setup IRQ routing */ + for (i = 0; i < 32; i++) { + pci_assign_irqs(0, i, qemu_i440fx_irqs); + } } static struct device_operations nb_operations = {

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New patch to review for coreboot: a942b9d qemu: remove vga hook
by Gerd Hoffmann 29 May '13

29 May '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3333 -gerrit commit a942b9da56b9d9d369f03f89a9b8e857604c93b4 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed May 29 14:53:03 2013 +0200 qemu: remove vga hook Extra care for the qemu vga should not be needed any more. Since release 0.12 qemu loads the vgabios into the PCI ROM bar, so everything works exactly like it does on real hardware. Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-x86/mainboard.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index 71bc893..ae92654 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -64,29 +64,3 @@ static const struct pci_driver nb_driver __pci_driver = { .vendor = 0x8086, .device = 0x1237, }; - -static void qemu_init(device_t dev) -{ - /* The VGA OPROM already lives at 0xc0000, - * force coreboot to use it. - */ - dev->on_mainboard = 1; - - /* Now do the usual initialization */ - pci_dev_init(dev); -} - -static struct device_operations vga_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = qemu_init, - .ops_pci = 0, -}; - -static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, - .vendor = 0x1013, - .device = 0x00b8, -}; -

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New patch to review for coreboot: 31c0f55 am335x: Build an omap style header and an image with it at the front.
by Gabe Black 29 May '13

29 May '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3332 -gerrit commit 31c0f55d90ec654224d58b3ae8909b529dd1d49b Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed May 29 16:42:35 2013 +0200 am335x: Build an omap style header and an image with it at the front. Loading on an OMAP SOC requires that the first sector of the image have a configuration header, and, when not an execute in place image, an additional header which describes how big the image is and where it should be loaded. This change adds some infrastructure to statically build that header using C code, and to paste the header onto the front of coreboot.rom in a new top level target file called MLO. The configuration header we're using is as inert as possible, in line with what U-Boot is doing. I think it could be used to give additional configuration parameters to the built-in ROM on the SOC, but we don't need to do that, and there didn't seem to be any actual documnetation how to do that. Because the header is built from C and is defined per CPU, it would be possible to include extra settings in other CPUs if desired. Adding a new top level build target is a bit disruptive, but should be contained to the am335x directory and not interfere with other mainboards. Change-Id: I06d346a4050c20963b3c7c6e8a152070bf2d145a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 17 ++++++++++ src/cpu/ti/am335x/header.c | 72 ++++++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/header.h | 67 +++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/header.ld | 34 ++++++++++++++++++++ 4 files changed, 190 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 8c4c663..c1bbcf6 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -10,3 +10,20 @@ ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c ramstage-y += uart.c + +$(call add-class,omap-header) + +real-target: $(obj)/MLO + +header_ld = $(src)/cpu/ti/am335x/header.ld + +$(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -include $(obj)/config.h -o $@.tmp $< -T $(header_ld) + $(OBJCOPY) --only-section=".header" -O binary $@.tmp $@ + +$(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin + @printf " HEADER $(subst $(obj)/,,$(@))\n" + $(Q)cat $(obj)/omap-header.bin $(obj)/coreboot.rom > $@ + +omap-header-y += header.c diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c new file mode 100644 index 0000000..bd2f344 --- /dev/null +++ b/src/cpu/ti/am335x/header.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <stddef.h> +#include <stdint.h> + +#include "header.h" + +struct config_headers { + // The table of contents. + struct configuration_header_toc_item toc_chsettings; + struct configuration_header_toc_item toc_end; + + // An inert instance of chsettings. + struct configuration_header_settings chsettings; +} __attribute__((packed)); + +struct omap_image_headers { + union { + struct config_headers config_headers; + uint8_t bytes[512]; + }; + struct gp_device_header image_header; +}; + +struct omap_image_headers headers __attribute__((section(".header"))) = { + .config_headers = { + .toc_chsettings = { + .start = offsetof(struct omap_image_headers, + config_headers.chsettings), + .size = sizeof(struct configuration_header_settings), + .reserved = { 0, 0, 0 }, + .filename = "CHSETTINGS\0" + }, + .toc_end = { + .start = 0xffffffff, + .size = 0xffffffff, + .reserved = { 0xffffffff, 0xffffffff, 0xffffffff }, + .filename = { 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff } + }, + .chsettings = { + .key = 0xc0c0c0c1, + .valid = 0, + .version = 1, + .reserved = 0, + .flags = 0 + } + }, + .image_header = { + .size = CONFIG_ROM_SIZE, + .destination = CONFIG_BOOTBLOCK_BASE + } +}; diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h new file mode 100644 index 0000000..84afd35 --- /dev/null +++ b/src/cpu/ti/am335x/header.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_HEADER_H +#define __CPU_TI_AM335X_HEADER_H + +#include <stdint.h> + +struct configuration_header_toc_item { + // Offset from the start address of the TOC to the actual address of + // a section. + uint32_t start; + + // Size of a section. + uint32_t size; + + // Reserved. + uint32_t reserved[3]; + + // 12-character name of a section, including the zero (\0) terminator. + char filename[12]; +} __attribute__((packed)); + +struct configuration_header_settings { + // Key used for section verification. + uint32_t key; + + // Enables or disables the section. + // 00h: Disable. + // Other: Enable. + uint8_t valid; + + // Configuration header version. + uint8_t version; + + // Reserved. + uint16_t reserved; + + // Flags. It's not clear what this is used for. + uint32_t flags; +} __attribute__((packed)); + +struct gp_device_header { + // Size of the image. + uint32_t size; + + // Address to store the image/code entry point. + uint32_t destination; +} __attribute__((packed)); + +#endif diff --git a/src/cpu/ti/am335x/header.ld b/src/cpu/ti/am335x/header.ld new file mode 100644 index 0000000..33c10e1 --- /dev/null +++ b/src/cpu/ti/am335x/header.ld @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +TARGET(binary) +SECTIONS +{ + .header : { + *(.header); + } + + /DISCARD/ : { + *(*) + } +}

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coreboot-gerrit May 2013