coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 855ff15 AMD Llano, Brazos boards: Use `sizeof(var)` to get its size
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3248 -gerrit commit 855ff15137ba9495ee08c379cdb2bb16ee1c52a9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 10:06:47 2013 +0200 AMD Llano, Brazos boards: Use `sizeof(var)` to get its size Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« Testing on the ASRock E350M1, no regressions were noticed. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/south_station/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/union_station/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 20 +++++++++----------- .../lippert/frontrunner-af/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 20 +++++++++----------- 8 files changed, 72 insertions(+), 88 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index c1fc77f..c64e523 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -108,9 +108,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 4 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -123,30 +121,30 @@ OemCustomizeInitEarly ( BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 4; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 4, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index fa909d2..3cd69f1 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index d0fd71b..a8511ea 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -116,9 +116,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -131,30 +129,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index a42d056..1639393 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -126,9 +126,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 6; + AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -141,30 +139,30 @@ OemCustomizeInitEarly ( LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Llano); LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (LlanoPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Llano), &InitEarly->StdHeader); LibAmdMemFill (LlanoPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (LlanoPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 98dd995..829b6c9 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -118,9 +118,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -133,30 +131,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index ee25ac9..50a8db9 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -118,9 +118,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -133,30 +131,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index 9bd9958..9724be1 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index 772ea53..61318b1 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;

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Patch set updated for coreboot: c01c148 Asus F2A85-M: Fix the _CRS PCI0 bus info
by Paul Menzel 28 May '13

28 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3320 -gerrit commit c01c14831f27d7a37c6fd2b9f530c68d4dfc5c2b Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 20:39:18 2013 +0200 Asus F2A85-M: Fix the _CRS PCI0 bus info On Asus F2A85-M, the Linux kernel complains that the _CRS method does not specify the number of PCI busses. [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS Just put there 256. This should be part of re-factoring of the whole ACPI stuff. The same change was already done for the AMD Brazos (SB800) boards, based on commit »Persimmon DSDT: Add secondary bus range to PCI0« (4733c647) [1]. [1] http://review.coreboot.org/2592 Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/dsdt.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index d9f8fa4..e98b6b3 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -1307,6 +1307,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,

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Patch set updated for coreboot: 3cd0f1d AMD Geode LX: add get_top_of_ram()
by Christian Gmeiner 28 May '13

28 May '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3322 -gerrit commit 3cd0f1d471c01ce879403f019e0892aea4caf259 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Tue May 28 17:09:29 2013 +0200 AMD Geode LX: add get_top_of_ram() get_top_of_ram() is needed for EARLY_CBMEM_INIT. We are reading the RCONF_DEFAULT_MSR (0x1808) msr. It contains SYSTOP [27:8], which is the top of system memory that is available for general processor use. Change-Id: Iadde6aab85ab2adc526f1ef3c5fc22e0f5b06d51 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/northbridge/amd/lx/raminit.c | 7 +++++++ src/northbridge/amd/lx/raminit.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 9a53e9e..4ab19e7 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -774,3 +774,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_info("RAM DLL lock\n"); } + +unsigned long get_top_of_ram(void) +{ + msr_t msr = rdmsr(CPU_RCONF_DEFAULT); + uint32_t systop = (msr.lo & 0xFFFFF00) >> 7; + return (unsigned long)systop; +} diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h index 3d4d4c6..8c11525 100644 --- a/src/northbridge/amd/lx/raminit.h +++ b/src/northbridge/amd/lx/raminit.h @@ -28,5 +28,6 @@ struct mem_controller { }; void sdram_initialize(int controllers, const struct mem_controller *ctrl); +unsigned long get_top_of_ram(void); #endif

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Patch set updated for coreboot: 73fa455 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3324 -gerrit commit 73fa455a58299b7fbd4210b57d60e1440922478e Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

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Patch set updated for coreboot: e3f8602 PC Engines ALIX.1C: Add CMOS defaults.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3323 -gerrit commit e3f8602e478fecac8f9a5bc52e9f33f794d30dc6 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 2 ++ src/mainboard/pcengines/alix1c/cmos.default | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..fab8710 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default new file mode 100644 index 0000000..189c691 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -0,0 +1,11 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0x7f

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Patch set updated for coreboot: 77c3800 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3324 -gerrit commit 77c3800377f3db6c1aef3a2ca44c49f301c7f834 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: TODO: test at runtime. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

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Patch set updated for coreboot: 497eedc Provide sane Kconfig default for cmos.default.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3223 -gerrit commit 497eedc384492f02cf6b4fa2b60d5c04a2f1ef61 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue May 28 13:46:12 2013 +0200 Provide sane Kconfig default for cmos.default. Without that fix we have with CONFIG_USE_OPTION_TABLE: OPTION cmos_layout.bin build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c That log was captured with make V=1 but the error also appear with make. This commit was tested on the PC Engines ALIX.1C with the following commit: PC Engines ALIX.1C: Add CMOS defaults. Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..c7b2434 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,6 +81,7 @@ config HAVE_CMOS_DEFAULT config CMOS_DEFAULT_FILE string + default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT config BOOTBLOCK_SOUTHBRIDGE_INIT

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New patch to review for coreboot: b337a67 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3324 -gerrit commit b337a675daf9c1163ab4d3c37f95ab6fbe1c0f47 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: TODO: test at runtime. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

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New patch to review for coreboot: a917917 PC Engines ALIX.1C: Add CMOS defaults.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3323 -gerrit commit a917917d2208ceb6c5772172cebb37cbc3bb0a87 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 2 ++ src/mainboard/pcengines/alix1c/cmos.default | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..fab8710 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default new file mode 100644 index 0000000..189c691 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -0,0 +1,11 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0x7f

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Patch set updated for coreboot: 177b6e9 Provide sane Kconfig default for cmos.default.
by Denis Carikli 28 May '13

28 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3223 -gerrit commit 177b6e91421e40d793e89366459f4794d2c444f2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue May 28 13:46:12 2013 +0200 Provide sane Kconfig default for cmos.default. This commit was tested on the PC Engines ALIX.1C with the following commit: PC Engines ALIX.1C: Add CMOS defaults. Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..c7b2434 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,6 +81,7 @@ config HAVE_CMOS_DEFAULT config CMOS_DEFAULT_FILE string + default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT config BOOTBLOCK_SOUTHBRIDGE_INIT

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coreboot-gerrit May 2013