Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3317
-gerrit
commit 8258c93db257065e2c6f59722e80b7e3a4a6bad6
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Mon May 27 16:12:00 2013 +0200
Asus F2A85-M: Activate the IOMMU support
Active the IOMMU support for Asus F2A85-M.
Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/mainboard/asus/f2a85-m/buildOpts.c | 2 +-
src/mainboard/asus/f2a85-m/devicetree.cb | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 7f893f9..4080e8b 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -171,7 +171,7 @@
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
-#define BLDCFG_IOMMU_SUPPORT FALSE
+#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 0014381..1cc610e 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIE SLOT0 x16 blue
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3314
-gerrit
commit 210bfa473212961fcb62734393ed3d6c8de91112
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Mon May 27 16:06:43 2013 +0200
fam15h: Add IOMMU BAR allocation
For IOMMU we need to allocate the 512KB BAR in non-standard
location. Use standard allocator for that, limit the BAR
to 32-bits to be compatible with older systems.
Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/include/device/pci_ids.h | 1 +
src/northbridge/amd/agesa/family15tn/Makefile.inc | 1 +
src/northbridge/amd/agesa/family15tn/iommu.c | 74 +++++++++++++++++++++++
3 files changed, 76 insertions(+)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index e9e5ab7..b455907 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -287,6 +287,7 @@
#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600
#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
+#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419
#define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
#define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380
diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc
index b609ee6..afec3c0 100644
--- a/src/northbridge/amd/agesa/family15tn/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc
@@ -20,6 +20,7 @@
romstage-y += fam15tn_callouts.c
romstage-y += dimmSpd.c
+ramstage-y += iommu.c
ramstage-y += northbridge.c
ramstage-y += fam15tn_callouts.c
ramstage-y += dimmSpd.c
diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c
new file mode 100644
index 0000000..7aeca49
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15tn/iommu.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <lib.h>
+
+static void iommu_read_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
+
+ /* Add an extra subtractive resource for both memory and I/O. */
+ res = new_resource(dev, 0x44);
+ res->size = 512 * 1024;
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffff; /* 4G */
+ res->flags = IORESOURCE_MEM;
+}
+
+static void iommu_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ pci_dev_set_resources(dev);
+
+ res = find_resource(dev, 0x44);
+ /* Remember this resource has been stored */
+ res->flags |= IORESOURCE_STORED;
+ /* For now, do only 32-bit space allocation */
+ pci_write_config32(dev, 0x48, 0x0);
+ pci_write_config32(dev, 0x44, res->base | 1 << 1);
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations iommu_ops = {
+ .read_resources = iommu_read_resources,
+ .set_resources = iommu_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver iommu_driver __pci_driver = {
+ .ops = &iommu_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU,
+};
the following patch was just integrated into master:
commit e4e8e090fa36cb3a098e1ddf0ea44c796c140572
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Mar 31 13:51:37 2013 +0200
util/inteltool: Add support for mobile 5 chipset
Dump registers on mobile 5. Successfully tested on X201.
Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/2993 for details.
-gerrit
Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3304
-gerrit
commit 83b0d43286df43f5260356ea064e5c7f4c0a228a
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Sun May 26 18:24:41 2013 +0200
i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c
Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
src/southbridge/intel/i82801gx/smihandler.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 193e96f..c4c6c70 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -20,6 +20,7 @@
*/
#include <types.h>
+#include <arch/hlt.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
@@ -345,6 +346,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
*/
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
+ /* Make sure to stop executing code here for S3/S4/S5 */
+ if (slp_typ > 1)
+ hlt();
/* In most sleep states, the code flow of this function ends at
* the line above. However, if we entered sleep state S1 and wake
* up again, we will continue to execute code in this function.