coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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593 discussions

New patch to review for coreboot: 83b0d43 i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c
by Denis Carikli 26 May '13

26 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3304 -gerrit commit 83b0d43286df43f5260356ea064e5c7f4c0a228a Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 26 18:24:41 2013 +0200 i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smihandler.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 193e96f..c4c6c70 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -20,6 +20,7 @@ */ #include <types.h> +#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -345,6 +346,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat */ outl(reg32 | SLP_EN, pmbase + PM1_CNT); + /* Make sure to stop executing code here for S3/S4/S5 */ + if (slp_typ > 1) + hlt(); /* In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function.

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New patch to review for coreboot: c9c7090 southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.
by Denis Carikli 26 May '13

26 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3303 -gerrit commit c9c7090e3355eabadf883bf54dad54d569fed58d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 26 18:12:54 2013 +0200 southbridge: i82801gx: smihandler.c: Correct outl->outw mistake. This mistake was spoted by comparison with the src/southbridge/intel/bd82x6x/smihandler.c file. Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smihandler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f199b84..193e96f 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -448,7 +448,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ { u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); - outl(reg16, pmbase + ALT_GP_SMI_STS); + outw(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN);

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Patch set updated for coreboot: 077eeca Lenovo ThinkPad X60: Add support for TSEG
by Denis Carikli 26 May '13

26 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3283 -gerrit commit 077eecac02987a4743b6444dcb30cc2614edad63 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri May 24 14:02:15 2013 +0200 Lenovo ThinkPad X60: Add support for TSEG The machine booted correctly under the parabola GNU/Linux distribution. Change-Id: I9717196e0c524cadff77ba78271cdb6fe627b014 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..729e208 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT + select SMM_TSEG config MAINBOARD_DIR string @@ -54,4 +55,8 @@ config MAX_CPUS int default 2 +config SMM_TSEG_SIZE + hex + default 0x100000 + endif

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Patch set updated for coreboot: 55683fb northbridge/intel/i945: Add TSEG Enabling support.
by Denis Carikli 26 May '13

26 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3282 -gerrit commit 55683fb38609a0402ce4f564733188b7779ff414 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 23 23:36:08 2013 +0200 northbridge/intel/i945: Add TSEG Enabling support. The resource part of that patch is based on the following commit: e6c3b1d30d3fa88af6da6fcc115aa6cba3c55d1c (haswell: include TSEG region in cacheable memory) Change-Id: I11fb5cb4083850ab0b1dc7cca86a59760aafbd17 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/cpu/x86/smm/smmhandler_tseg.S | 31 ++++++++++++++++- src/cpu/x86/smm/smmrelocate.S | 31 +++++++++++++++-- src/northbridge/intel/i945/Kconfig | 4 +++ src/northbridge/intel/i945/Makefile.inc | 1 + src/northbridge/intel/i945/northbridge.c | 58 +++++++++++++++++++------------- src/northbridge/intel/i945/raminit.c | 34 +++++++++++++++++++ src/northbridge/intel/i945/raminit.h | 9 +++++ src/northbridge/intel/i945/smi.c | 37 ++++++++++++++++++++ 8 files changed, 178 insertions(+), 27 deletions(-) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index eb5d63c..a9cff6c 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -63,6 +63,7 @@ #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL #include <northbridge/intel/haswell/haswell.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_I945 #else #error "Northbridge must define TSEG_BAR." #endif @@ -82,8 +83,22 @@ * All the bad magic is not all that bad after all. */ smm_handler_start: +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax + movl %eax, %edx +#else movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ +#endif andl $~1, %edx /* Remove lock bit */ /* Obtain lock */ @@ -195,8 +210,22 @@ smm_prot_start: call smi_handler /* Release lock */ +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax + movl %eax, %ebx +#else movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ +#endif andl $~1, %ebx /* Remove lock bit */ addl $(smm_lock), %ebx movw $SMI_UNLOCKED, %ax diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16d4b9f..8c20579 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -48,6 +48,7 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_I945 #else #error "Northbridge must define TSEG_BAR." #endif @@ -148,8 +149,21 @@ smm_relocate: shl $10, %edx #if CONFIG_SMM_TSEG +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax +#else movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ +#endif andl $~1, %eax /* Remove lock bit */ #else movl $0xa0000, %eax @@ -166,8 +180,21 @@ smm_relocate: jnc skip_smrr /* TSEG base */ +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax +#else movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ +#endif andl $~1, %eax /* Remove lock bit */ movl %eax, %ebx diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index aec3e33..52cd0f6 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -66,4 +66,8 @@ config CHECK_SLFRCS_ON_RESUME On other boards the check always creates a false positive, effectively making it impossible to resume. +config I915_UMA_SIZE + hex + default 0x800000 + endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 92a8849..6fea3e0 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -27,3 +27,4 @@ romstage-y += errata.c romstage-y += debug.c smm-y += udelay.c +smm-y += smi.c diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..5cd32f6 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -88,6 +88,9 @@ static void pci_domain_set_resources(device_t dev) uint16_t reg16; unsigned long long tomk, tomk_stolen; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; +#if CONFIG_SMM_TSEG + struct resource *resource; +#endif /* Can we find out how much memory we can use at most * this way? @@ -105,6 +108,29 @@ static void pci_domain_set_resources(device_t dev) tomk_stolen = tomk; /* Note: subtract IGD device and TSEG */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + if (!(reg16 & 2)) { + int uma_size = 0; + printk(BIOS_DEBUG, "IGD decoded, subtracting "); + reg16 >>= 4; + reg16 &= 7; + switch (reg16) { + case 1: + uma_size = 1024; + break; + case 3: + uma_size = 8192; + break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + tomk_stolen -= uma_size; + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk_stolen * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + } + reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); if (reg8 & 1) { int tseg_size = 0; @@ -131,29 +157,6 @@ static void pci_domain_set_resources(device_t dev) tseg_memory_size = tseg_size * 1024ULL; } - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - if (!(reg16 & 2)) { - int uma_size = 0; - printk(BIOS_DEBUG, "IGD decoded, subtracting "); - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } - - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk_stolen -= uma_size; - - /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk_stolen * 1024ULL; - uma_memory_size = uma_size * 1024ULL; - } - /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -173,8 +176,15 @@ static void pci_domain_set_resources(device_t dev) /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; +#if CONFIG_SMM_TSEG + resource = new_resource(dev, 8); + resource->base = tseg_memory_base; + resource->size = tseg_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; +#endif } - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..edd6b6a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3052,6 +3052,36 @@ static void sdram_setup_processor_side(void) MCHBAR32(SLPCTL) |= (1 << 8); } +#if CONFIG_SMM_TSEG +static void sdram_enable_tseg(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM); + reg8 |= (1 << 0); /* TSEG Enable */ + + switch(CONFIG_SMM_TSEG_SIZE){ + + case 0x100000: + reg8 &= ~((1<<2)|(1<<1)); + break; + case 0x200000: + reg8 &= ~(1<<1); + reg8 |= (1<<2); + break; + case 0x800000: + reg8 |= (1<<2)|(1<<1); + break; + default: + /* it should not happen because we guard + * ainst that in the raminit.h header + */ + printk(BIOS_ERR, "Invalid TSEG size!\n"); + } + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAM, reg8); +} +#endif + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -3180,6 +3210,10 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Enable Periodic RCOMP */ sdram_enable_rcomp(); +#if CONFIG_SMM_TSEG + sdram_enable_tseg(); +#endif + /* Tell ICH7 that we're done */ reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2); reg8 &= ~(1 << 7); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..7f08af5 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -75,5 +75,14 @@ void udelay(u32 us); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void); + +#if CONFIG_SMM_TSEG +#if ! (CONFIG_SMM_TSEG_SIZE == 0x100000 || \ + CONFIG_SMM_TSEG_SIZE == 0x200000 || \ + CONFIG_SMM_TSEG_SIZE == 0x800000) +#error Invalid TSEG size +#endif +#endif + #endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i945/smi.c b/src/northbridge/intel/i945/smi.c new file mode 100644 index 0000000..0993b12 --- /dev/null +++ b/src/northbridge/intel/i945/smi.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#include <types.h> +#include <arch/io.h> +#include <cpu/x86/smm.h> +#include "i945.h" + +#if CONFIG_SMM_TSEG +static u32 tseg_base = 0; +u32 smi_get_tseg_base(void) +{ + if (!tseg_base) + tseg_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) - + CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE; + return tseg_base; +} +#endif +

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Patch set updated for coreboot: 07c28f2 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
by Denis Carikli 26 May '13

26 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3281 -gerrit commit 07c28f2a8eaac0e383ccb67cddf223ebbe354cbc Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri May 24 03:37:01 2013 +0200 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG Without that fix, and with CONFIG_SMM_TSEG, we have: src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep': src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1 The fix is modelled after src/cpu/x86/smm/smihandler.c which ifdefs smi_release_lock(). Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smihandler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index c4c6c70..5517437 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -333,12 +333,14 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } +#if !CONFIG_SMM_TSEG /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore * will never be unlocked because the next outl will switch off the CPU. * This might open a small race between the smi_release_lock() and the outl() * for other SMI handlers. Not sure if this could cause trouble. */ if (slp_typ == 5) smi_release_lock(); +#endif /* Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the

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New patch to review for coreboot: 145ee96 util/cbmem: Fix format string in cbmem.c
by Nico Huber 26 May '13

26 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3301 -gerrit commit 145ee965dc7c49315126493afb5f57ccdd4940ae Author: Nico Huber <nico.huber(a)secunet.com> Date: Sun May 26 18:17:54 2013 +0200 util/cbmem: Fix format string in cbmem.c Use PRIx64 to print a u64 instead of "llx". Fixes the following error: cbmem.c: In Funktion »parse_cbtable«: cbmem.c:135:2: Fehler: Format »%llx« erwartet Argumenttyp »long long unsigned int«, aber Argument 2 hat Typ »u64« [-Werror=format] Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/cbmem/cbmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..74e0fd4 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <inttypes.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -132,7 +133,7 @@ static int parse_cbtable(u64 address) int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */

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Patch merged into coreboot/master: 3c7e939 beaglebone: initial Kconfig and Makefiles
by gerrit＠coreboot.org 26 May '13

26 May '13

the following patch was just integrated into master: commit 3c7e939c3e18b3d286c084ff95266611a0150ca1 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sun May 26 07:15:57 2013 -0700 beaglebone: initial Kconfig and Makefiles Initial structure of Beaglebone port Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3279 for details. -gerrit

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Patch merged into coreboot/master: b460a66 Get buildgcc to behave reasonably with the -p choice.
by gerrit＠coreboot.org 26 May '13

26 May '13

the following patch was just integrated into master: commit b460a66aa96a42349ebbd2e6e8d450787437e0e3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun May 26 05:33:35 2013 -0700 Get buildgcc to behave reasonably with the -p choice. buildgcc has many wrong choices, and two right ones, but you would never guess that. It's even more frustrating when it spends lots of time building a full tool chain and you find out it's not the one you wanted and, still worse, you've forgotten what it does want and, even worse, it won't f-ing tell you what the two right choices are!. Have it tell you when you've done something wrong, and have it make reasonable decisions when you say things like -p arm instead of -p armv7a-eabi This change lowers my blood pressure 10 points. Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/3292 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3292 for details. -gerrit

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Patch merged into coreboot/master: ac6ea04 Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
by gerrit＠coreboot.org 26 May '13

26 May '13

the following patch was just integrated into master: commit ac6ea04b627e9a045a1600fa36e44150e9e5622b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 29 23:21:07 2013 +0200 Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console support by copying GNUtoo’s commit for the Lenovo ThinkPad X60. commit 4560ca5003fe38a066616e8de1a8a414284750fd Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support. Reviewed-on: http://review.coreboot.org/3142 Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3187 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo(a)no-log.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Nico Huber <nico.huber(a)secunet.com> See http://review.coreboot.org/3187 for details. -gerrit

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Patch set updated for coreboot: a4134f4 beaglebone: initial Kconfig and Makefiles
by Gabe Black 26 May '13

26 May '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3279 -gerrit commit a4134f47680a90c020a4da7ce7952dfd5fa49d1a Author: Gabe Black <gabeblack(a)chromium.org> Date: Sun May 26 07:15:57 2013 -0700 beaglebone: initial Kconfig and Makefiles Initial structure of Beaglebone port Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/ti/Kconfig | 11 +++ src/cpu/ti/Makefile.inc | 1 + src/cpu/ti/am335x/Kconfig | 79 +++++++++++++++ src/cpu/ti/am335x/Makefile.inc | 12 +++ src/cpu/ti/am335x/bootblock.c | 33 +++++++ src/cpu/ti/am335x/dmtimer.c | 29 ++++++ src/cpu/ti/am335x/dmtimer.h | 30 ++++++ src/cpu/ti/am335x/monotonic_timer.c | 57 +++++++++++ src/cpu/ti/am335x/nand.c | 26 +++++ src/cpu/ti/am335x/timer.c | 51 ++++++++++ src/cpu/ti/am335x/uart.c | 137 ++++++++++++++++++++++++++ src/cpu/ti/am335x/uart.h | 36 +++++++ src/mainboard/Kconfig | 3 + src/mainboard/ti/Kconfig | 37 ++++++++ src/mainboard/ti/beaglebone/Kconfig | 153 ++++++++++++++++++++++++++++++ src/mainboard/ti/beaglebone/Makefile.inc | 22 +++++ src/mainboard/ti/beaglebone/bootblock.c | 31 ++++++ src/mainboard/ti/beaglebone/devicetree.cb | 22 +++++ src/mainboard/ti/beaglebone/mainboard.c | 23 +++++ src/mainboard/ti/beaglebone/romstage.c | 37 ++++++++ 22 files changed, 832 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ed7d6ab..dd28cb7 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -5,6 +5,7 @@ if ARCH_ARMV7 source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig +source src/cpu/ti/Kconfig endif # ARCH_ARM diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 8d93756..25ef424 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -5,6 +5,7 @@ subdirs-y += amd subdirs-y += armltd subdirs-y += intel subdirs-y += samsung +subdirs-y += ti subdirs-y += via subdirs-y += x86 diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig new file mode 100644 index 0000000..c82c290 --- /dev/null +++ b/src/cpu/ti/Kconfig @@ -0,0 +1,11 @@ +config CPU_TI_AM335X + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_EARLY_CONSOLE + bool + default n + +if CPU_TI_AM335X +source src/cpu/ti/am335x/Kconfig +endif diff --git a/src/cpu/ti/Makefile.inc b/src/cpu/ti/Makefile.inc new file mode 100644 index 0000000..64b22f6 --- /dev/null +++ b/src/cpu/ti/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_TI_AM335X) += am335x diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig new file mode 100644 index 0000000..c4ef8f1 --- /dev/null +++ b/src/cpu/ti/am335x/Kconfig @@ -0,0 +1,79 @@ +config BOOTBLOCK_CPU_INIT + string + default "cpu/ti/am335x/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# Example SRAM/iRAM map for Exynos5250 platform: +# +# 0x0202_3400: bootblock, assume up to 32KB in size +# 0x0203_0000: romstage, assume up to 128KB in size. +# 0x0207_8000: stack pointer + +# FIXME: find out where romboot places ml0/coreboot +config BOOTBLOCK_BASE + hex + default 0xdeadbeef + +#config ROMSTAGE_BASE +# hex +# default 0x02030000 +# +# FIXME: this is bullshit. +config ROMSTAGE_SIZE + hex + default 0xa000 + +# Stack may reside in either IRAM or DRAM. We will define it to live +# at the top of IRAM for now. +# +# Stack grows downward, push operation stores register contents in +# consecutive memory locations ending just below SP +config STACK_TOP + hex + default 0x02078000 + +config STACK_BOTTOM + hex + default 0x02077000 + +config STACK_SIZE + hex + default 0x1000 + +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + +## TODO Change this to some better address not overlapping bootblock when +## cbfstool supports creating header in arbitrary location. +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40 + +## TODO We may probably move this to board-specific implementation files instead +## of KConfig values. +#config CBFS_CACHE_ADDRESS +# hex "memory address to put CBFS cache data" +# default 0x02060000 +# +#config CBFS_CACHE_SIZE +# hex "size of CBFS cache data" +# default 0x000017000 + +# FIXME: other magic numbers that should probably go away +config XIP_ROM_SIZE + hex + default ROMSTAGE_SIZE + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +# FIXME: this can probably be smaller +config COREBOOT_TABLES_SIZE + hex + default 0x800 diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc new file mode 100644 index 0000000..8c4c663 --- /dev/null +++ b/src/cpu/ti/am335x/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += dmtimer.c +bootblock-y += nand.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c + +romstage-y += nand.c +romstage-y += uart.c + +ramstage-y += dmtimer.c +ramstage-y += monotonic_timer.c +ramstage-y += nand.c +ramstage-y += timer.c +ramstage-y += uart.c diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c new file mode 100644 index 0000000..e9434a1 --- /dev/null +++ b/src/cpu/ti/am335x/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> + +#include <arch/cache.h> + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + uint32_t sctlr; + + /* enable dcache */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C; + write_sctlr(sctlr); +} diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/cpu/ti/am335x/dmtimer.c new file mode 100644 index 0000000..6a55d9d --- /dev/null +++ b/src/cpu/ti/am335x/dmtimer.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "dmtimer.h" + +void dmtimer_start(int num) +{ +} + +uint64_t dmtimer_raw_value(int num) +{ + return 0; +} diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/cpu/ti/am335x/dmtimer.h new file mode 100644 index 0000000..12ca438 --- /dev/null +++ b/src/cpu/ti/am335x/dmtimer.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CPU_TI_AM335X_DMTIMER_H__ +#define __CPU_TI_AM335X_DMTIMER_H__ + +#include <stdint.h> + +#define OSC_HZ 24000000 + +void dmtimer_start(int num); +uint64_t dmtimer_raw_value(int num); + +#endif diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c new file mode 100644 index 0000000..9a9083c --- /dev/null +++ b/src/cpu/ti/am335x/monotonic_timer.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <delay.h> +#include <timer.h> + +#include "dmtimer.h" + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint64_t last_value; +} mono_counter; + +static const uint32_t clocks_per_usec = OSC_HZ/1000000; + +void timer_monotonic_get(struct mono_time *mt) +{ + uint64_t current_tick; + uint64_t usecs_elapsed; + + if (!mono_counter.initialized) { + init_timer(); + mono_counter.last_value = dmtimer_raw_value(0); + mono_counter.initialized = 1; + } + + current_tick = dmtimer_raw_value(0); + usecs_elapsed = (current_tick - mono_counter.last_value) / + clocks_per_usec; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +} diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c new file mode 100644 index 0000000..ddab389 --- /dev/null +++ b/src/cpu/ti/am335x/nand.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + /* FIXME: add support for reading coreboot from NAND */ + return 0; +} diff --git a/src/cpu/ti/am335x/timer.c b/src/cpu/ti/am335x/timer.c new file mode 100644 index 0000000..07b162a --- /dev/null +++ b/src/cpu/ti/am335x/timer.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <console/console.h> +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ +} + +/* delay x useconds */ +void udelay(unsigned usec) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, usec); + + if (mono_time_after(&current, &end)) { + printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", + usec); + /* There's not much we can do if usec is too big. Use a long, + * paranoid delay value and hope for the best... */ + end = current; + mono_time_add_usecs(&end, USECS_PER_SEC); + } + + while (mono_time_before(&current, &end)) + timer_monotonic_get(&current); +} diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c new file mode 100644 index 0000000..fdf5c05 --- /dev/null +++ b/src/cpu/ti/am335x/uart.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * based on drivers/serial/s3c64xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <types.h> +#include <uart.h> +#include <arch/io.h> + +#include <console/console.h> /* for __console definition */ + +#include <cpu/ti/am335x/uart.h> + +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static void am335x_uart_init_dev(void) +{ + /* FIXME: implement this + * ref: section 19.4.1.1.1 for reset + * ref: section 19.4.1.1.2 for FIFO, skip DMA + * ref: section 19.4.1.1.3 for baud rate, skip + * interrupts and protocol stuff. + * */ +#if 0 + struct s5p_uart *uart = (struct s5p_uart *)base_port; + + // TODO initialize with correct peripheral id by base_port. + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + + /* enable FIFOs */ + writel(0x1, &uart->ufcon); + writel(0, &uart->umcon); + /* 8N1 */ + writel(0x3, &uart->ulcon); + /* No interrupts, no DMA, pure polling */ + writel(0x245, &uart->ucon); + + serial_setbrg_dev(); +#endif +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +static unsigned char am335x_uart_rx_byte(void) +{ + /* FIXME: stub */ +#if 0 + struct s5p_uart *uart = (struct s5p_uart *)base_port; + + /* wait for character to arrive */ + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { + if (exynos5_uart_err_check(0)) + return 0; + } + + return readb(&uart->urxh) & 0xff; +#endif + return 0xaa; +} + +/* + * Output a single byte to the serial port. + */ +static void am335x_uart_tx_byte(unsigned char data) +{ + /* FIXME: stub */ +#if 0 + struct s5p_uart *uart = (struct s5p_uart *)base_port; + + /* wait for room in the tx FIFO */ + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { + if (exynos5_uart_err_check(1)) + return; + } + + writeb(data, &uart->utxh); +#endif +} + +uint32_t uartmem_getbaseaddr(void) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + +#if !defined(__PRE_RAM__) +static const struct console_driver exynos5_uart_console __console = { + .init = am335x_uart_init_dev, + .tx_byte = am335x_uart_tx_byte, + .rx_byte = am335x_uart_rx_byte, +}; +#else +void uart_init(void) +{ + am335x_uart_init_dev(); +} + +unsigned char uart_rx_byte(void) +{ + return am335x_uart_rx_byte(); +} + +void uart_tx_byte(unsigned char data) +{ + am335x_uart_tx_byte(data); +} + +void uart_tx_flush(void) { +} +#endif diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h new file mode 100644 index 0000000..b642e9c --- /dev/null +++ b/src/cpu/ti/am335x/uart.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 The ChromiumOS Authors + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file is based off of arch/arm/include/asm/arch-exynos5/uart.h + * from u-boot. + */ + +#ifndef __AM335X_UART_H_ +#define __AM335X_UART_H + +#define AM335X_UART0_BASE 0x44e09000 +#define AM335X_UART1_BASE 0x48020000 +#define AM335X_UART2_BASE 0x48024000 +#define AM335X_UART3_BASE 0x481A6000 +#define AM335X_UART4_BASE 0x481A8000 +#define AM335X_UART5_BASE 0x481AA000 + +#endif diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 3ca21ff..1e5d4bd 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -120,6 +120,8 @@ config VENDOR_TECHNOLOGIC bool "Technologic" config VENDOR_TELEVIDEO bool "TeleVideo" +config VENDOR_TI + bool "TI" config VENDOR_THOMSON bool "Thomson" config VENDOR_TRAVERSE @@ -194,6 +196,7 @@ source "src/mainboard/technexion/Kconfig" source "src/mainboard/technologic/Kconfig" source "src/mainboard/televideo/Kconfig" source "src/mainboard/thomson/Kconfig" +source "src/mainboard/ti/Kconfig" source "src/mainboard/traverse/Kconfig" source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" diff --git a/src/mainboard/ti/Kconfig b/src/mainboard/ti/Kconfig new file mode 100644 index 0000000..c4cd8c3 --- /dev/null +++ b/src/mainboard/ti/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if VENDOR_TI + +# Auto select common options +choice + prompt "Mainboard model" + +config BOARD_TI_BEAGLEBONE + bool "Beaglebone" + +endchoice + +source "src/mainboard/ti/beaglebone/Kconfig" + +config MAINBOARD_VENDOR + string + default "TI" + +endif # VENDOR_TI diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig new file mode 100644 index 0000000..97fdf48 --- /dev/null +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -0,0 +1,153 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_TI_BEAGLEBONE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_TI_AM335X + select HAVE_UART_MEMORY_MAPPED + # FIXME: This should be much smaller + select BOARD_ROMSIZE_KB_128 + +config MAINBOARD_DIR + string + default ti/beaglebone + +config MAINBOARD_PART_NUMBER + string + default "Beaglebone" + +config MAX_CPUS + int + default 1 + +config MAINBOARD_VENDOR + string + default "TI" + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/ti/beaglebone/bootblock.c" + +config DRAM_SIZE_MB + int + default 256 + +config NR_DRAM_BANKS + int + default 1 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART0 + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +config CONSOLE_SERIAL_UART4 + bool "UART4" + help + Serial console on UART4 + +config CONSOLE_SERIAL_UART5 + bool "UART5" + help + Serial console on UART5 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x44e09000 if CONSOLE_SERIAL_UART0 + default 0x48022000 if CONSOLE_SERIAL_UART1 + default 0x48024000 if CONSOLE_SERIAL_UART2 + default 0x481a6000 if CONSOLE_SERIAL_UART3 + default 0x481a8000 if CONSOLE_SERIAL_UART4 + default 0x481aa000 if CONSOLE_SERIAL_UART5 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config I2C_MULTI_BUS + bool + default y + +#FIXME: get proper voltages + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +endif # BOARD_TI_BEAGLEBONE diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc new file mode 100644 index 0000000..c76cb37 --- /dev/null +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c + +#ramstage-y += ramstage.c diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c new file mode 100644 index 0000000..77e382d --- /dev/null +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <uart.h> +#include <console/console.h> + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + /* Start monotonic timer */ + //rtc_start(); + + console_init(); +} diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone/devicetree.cb new file mode 100644 index 0000000..f7b409c --- /dev/null +++ b/src/mainboard/ti/beaglebone/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip cpu/ti/am335x + device cpu_cluster 0 on end +end diff --git a/src/mainboard/ti/beaglebone/mainboard.c b/src/mainboard/ti/beaglebone/mainboard.c new file mode 100644 index 0000000..1717be4 --- /dev/null +++ b/src/mainboard/ti/beaglebone/mainboard.c @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* FIXME: this is a stub */ +void main(void) +{ +} diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c new file mode 100644 index 0000000..74eaaf2 --- /dev/null +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> + +#include <armv7.h> +#include <cbfs.h> +#include <common.h> + +#include <arch/stages.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); + + stage_exit(entry); +}

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coreboot-gerrit May 2013