coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 73412c2 Lenovo ThinkPad X60: Add support for TSEG
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3283 -gerrit commit 73412c2b460a5e9dafc0d7b19ad74d61035f7400 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri May 24 14:02:15 2013 +0200 Lenovo ThinkPad X60: Add support for TSEG The machine booted correctly under the parabola GNU/Linux distribution. Change-Id: I9717196e0c524cadff77ba78271cdb6fe627b014 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..729e208 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT + select SMM_TSEG config MAINBOARD_DIR string @@ -54,4 +55,8 @@ config MAX_CPUS int default 2 +config SMM_TSEG_SIZE + hex + default 0x100000 + endif

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Patch set updated for coreboot: 8d4843d northbridge/intel/i945: Add TSEG Enabling support.
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3282 -gerrit commit 8d4843da13169cc54cd30512d5edd6b0ab7e3c0c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 23 23:36:08 2013 +0200 northbridge/intel/i945: Add TSEG Enabling support. The resource part of that patch is based on the following commit: e6c3b1d30d3fa88af6da6fcc115aa6cba3c55d1c (haswell: include TSEG region in cacheable memory) Change-Id: I11fb5cb4083850ab0b1dc7cca86a59760aafbd17 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/cpu/x86/smm/smmhandler_tseg.S | 31 ++++++++++++++++- src/cpu/x86/smm/smmrelocate.S | 31 +++++++++++++++-- src/northbridge/intel/i945/Kconfig | 4 +++ src/northbridge/intel/i945/Makefile.inc | 1 + src/northbridge/intel/i945/northbridge.c | 58 +++++++++++++++++++------------- src/northbridge/intel/i945/raminit.c | 34 +++++++++++++++++++ src/northbridge/intel/i945/raminit.h | 9 +++++ src/northbridge/intel/i945/smi.c | 37 ++++++++++++++++++++ 8 files changed, 178 insertions(+), 27 deletions(-) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index eb5d63c..a9cff6c 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -63,6 +63,7 @@ #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL #include <northbridge/intel/haswell/haswell.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_I945 #else #error "Northbridge must define TSEG_BAR." #endif @@ -82,8 +83,22 @@ * All the bad magic is not all that bad after all. */ smm_handler_start: +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax + movl %eax, %edx +#else movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ +#endif andl $~1, %edx /* Remove lock bit */ /* Obtain lock */ @@ -195,8 +210,22 @@ smm_prot_start: call smi_handler /* Release lock */ +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax + movl %eax, %ebx +#else movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ +#endif andl $~1, %ebx /* Remove lock bit */ addl $(smm_lock), %ebx movw $SMI_UNLOCKED, %ax diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16d4b9f..8c20579 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -48,6 +48,7 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_I945 #else #error "Northbridge must define TSEG_BAR." #endif @@ -148,8 +149,21 @@ smm_relocate: shl $10, %edx #if CONFIG_SMM_TSEG +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax +#else movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ +#endif andl $~1, %eax /* Remove lock bit */ #else movl $0xa0000, %eax @@ -166,8 +180,21 @@ smm_relocate: jnc skip_smrr /* TSEG base */ +#if CONFIG_NORTHBRIDGE_INTEL_I945 + /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */ + movl $0x8000009c, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + inl %dx, %eax + + /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/ + subl $CONFIG_I915_UMA_SIZE, %eax + subl $CONFIG_SMM_TSEG_SIZE, %eax +#else movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ +#endif andl $~1, %eax /* Remove lock bit */ movl %eax, %ebx diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index aec3e33..52cd0f6 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -66,4 +66,8 @@ config CHECK_SLFRCS_ON_RESUME On other boards the check always creates a false positive, effectively making it impossible to resume. +config I915_UMA_SIZE + hex + default 0x800000 + endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 92a8849..6fea3e0 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -27,3 +27,4 @@ romstage-y += errata.c romstage-y += debug.c smm-y += udelay.c +smm-y += smi.c diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..5cd32f6 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -88,6 +88,9 @@ static void pci_domain_set_resources(device_t dev) uint16_t reg16; unsigned long long tomk, tomk_stolen; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; +#if CONFIG_SMM_TSEG + struct resource *resource; +#endif /* Can we find out how much memory we can use at most * this way? @@ -105,6 +108,29 @@ static void pci_domain_set_resources(device_t dev) tomk_stolen = tomk; /* Note: subtract IGD device and TSEG */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + if (!(reg16 & 2)) { + int uma_size = 0; + printk(BIOS_DEBUG, "IGD decoded, subtracting "); + reg16 >>= 4; + reg16 &= 7; + switch (reg16) { + case 1: + uma_size = 1024; + break; + case 3: + uma_size = 8192; + break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + tomk_stolen -= uma_size; + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk_stolen * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + } + reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); if (reg8 & 1) { int tseg_size = 0; @@ -131,29 +157,6 @@ static void pci_domain_set_resources(device_t dev) tseg_memory_size = tseg_size * 1024ULL; } - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - if (!(reg16 & 2)) { - int uma_size = 0; - printk(BIOS_DEBUG, "IGD decoded, subtracting "); - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } - - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk_stolen -= uma_size; - - /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk_stolen * 1024ULL; - uma_memory_size = uma_size * 1024ULL; - } - /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -173,8 +176,15 @@ static void pci_domain_set_resources(device_t dev) /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; +#if CONFIG_SMM_TSEG + resource = new_resource(dev, 8); + resource->base = tseg_memory_base; + resource->size = tseg_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; +#endif } - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..edd6b6a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3052,6 +3052,36 @@ static void sdram_setup_processor_side(void) MCHBAR32(SLPCTL) |= (1 << 8); } +#if CONFIG_SMM_TSEG +static void sdram_enable_tseg(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM); + reg8 |= (1 << 0); /* TSEG Enable */ + + switch(CONFIG_SMM_TSEG_SIZE){ + + case 0x100000: + reg8 &= ~((1<<2)|(1<<1)); + break; + case 0x200000: + reg8 &= ~(1<<1); + reg8 |= (1<<2); + break; + case 0x800000: + reg8 |= (1<<2)|(1<<1); + break; + default: + /* it should not happen because we guard + * ainst that in the raminit.h header + */ + printk(BIOS_ERR, "Invalid TSEG size!\n"); + } + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAM, reg8); +} +#endif + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -3180,6 +3210,10 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Enable Periodic RCOMP */ sdram_enable_rcomp(); +#if CONFIG_SMM_TSEG + sdram_enable_tseg(); +#endif + /* Tell ICH7 that we're done */ reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2); reg8 &= ~(1 << 7); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..7f08af5 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -75,5 +75,14 @@ void udelay(u32 us); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void); + +#if CONFIG_SMM_TSEG +#if ! (CONFIG_SMM_TSEG_SIZE == 0x100000 || \ + CONFIG_SMM_TSEG_SIZE == 0x200000 || \ + CONFIG_SMM_TSEG_SIZE == 0x800000) +#error Invalid TSEG size +#endif +#endif + #endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i945/smi.c b/src/northbridge/intel/i945/smi.c new file mode 100644 index 0000000..0993b12 --- /dev/null +++ b/src/northbridge/intel/i945/smi.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#include <types.h> +#include <arch/io.h> +#include <cpu/x86/smm.h> +#include "i945.h" + +#if CONFIG_SMM_TSEG +static u32 tseg_base = 0; +u32 smi_get_tseg_base(void) +{ + if (!tseg_base) + tseg_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) - + CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE; + return tseg_base; +} +#endif +

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Patch set updated for coreboot: bc929c8 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3281 -gerrit commit bc929c8f93b6dce1d6d1ec6b7a3805766243ba7d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri May 24 03:37:01 2013 +0200 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG Without that fix, and with CONFIG_SMM_TSEG, we have: src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep': src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1 The fix is modelled after src/cpu/x86/smm/smihandler.c which ifdefs smi_release_lock(). Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smihandler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f199b84..8e67f79 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -332,12 +332,14 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } +#if !CONFIG_SMM_TSEG /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore * will never be unlocked because the next outl will switch off the CPU. * This might open a small race between the smi_release_lock() and the outl() * for other SMI handlers. Not sure if this could cause trouble. */ if (slp_typ == 5) smi_release_lock(); +#endif /* Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the

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Patch set updated for coreboot: d728e59 southbridge/intel/i82801gx: Add support for CONFIG_SMM_TSEG
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3284 -gerrit commit d728e59c0e27dfd7a28f6c6d4a47bef9cd94db4f Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat May 25 13:42:43 2013 +0200 southbridge/intel/i82801gx: Add support for CONFIG_SMM_TSEG Change-Id: I795c112c2432d56681dace5cd1b1d23b1d361c0a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 5be2404..39570e5 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -29,6 +29,9 @@ #include <cpu/x86/smm.h> #include <string.h> #include "i82801gx.h" +#if CONFIG_NORTHBRIDGE_INTEL_I945 +#include "../../../northbridge/intel/i945/i945.h" +#endif extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_size; @@ -245,7 +248,13 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_SMM_TSEG + pmbase = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD); + pmbase -= CONFIG_I915_UMA_SIZE; + pmbase -= CONFIG_SMM_TSEG_SIZE; +#else pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; +#endif printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN);

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New patch to review for coreboot: 8e9dfd8 WIP: winbond/w83627dhg: ACPI code drop
by Nico Huber 25 May '13

25 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3288 -gerrit commit 8e9dfd85c48743d7516a6fb2f480141753f3bbf1 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri May 24 13:48:26 2013 +0200 WIP: winbond/w83627dhg: ACPI code drop An example how the ACPI framework can be used. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/superio/winbond/w83627dhg/acpi/superio.asl | 196 +++++++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl new file mode 100644 index 0000000..417d6fe --- /dev/null +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the W83627DHG SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x0 FDC Not implemented + * 0x1 PP Not implemented + * 0x2 UARTA Implemented, partially tested + * 0x3 UARTB UART only, partially tested + * 0x5 KBC Implemented, untested + * 0x6 SPI Not implemented + * 0x7 GPIO6 Not implemented + * 0x8 WDT0&PLED Not implemented + * 0x9 GPIO2-5 Not implemented + * 0xa ACPI Not implemented + * 0xb HWM Resources, PM only + * 0xc PECI&SST Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * W83627DHG_SHOW_UARTA If defined, UARTA will be exposed. + * W83627DHG_SHOW_UARTB If defined, UARTB will be exposed. + * W83627DHG_SHOW_KBC If defined, the KBC will be exposed. + * W83627DHG_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * W83627DHG_SHOW_HWMON If defined, the hardware monitor will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME W83627DHG +#include <superio/acpi/pnp.asl> + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83627DHG Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x22), + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + Offset (0x23), + IPD, 1, /* Immediate Chip Power Down */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + + Offset (0x74), + PNP_DMA0, 8, /* DMA */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) + Store (IPD, Local0) + EXIT_CONFIG_MODE () + If (Local0) { Return (2) } + Else { Return (0) } + } + + /* PM: Switch to D0 by setting IPD low */ + Method (_PS0) { + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) + Store (Zero, IPD) + EXIT_CONFIG_MODE () + } + + /* PM: Switch to D2 by setting IPD high */ + Method (_PS2) { + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) + Store (One, IPD) + EXIT_CONFIG_MODE () + } + +#ifdef W83627DHG_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef W83627DHG_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 3 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef W83627DHG_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef W83627DHG_SHOW_PS2M + #define SUPERIO_KBC_PS2M 1 +#endif + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef W83627DHG_SHOW_HWMON + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_PM_REG HWPW + #define SUPERIO_PNP_PM_LDN PNP_NO_LDN_CHANGE + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 1 + #include <superio/acpi/pnp_generic.asl> +#endif +}

1 0

New patch to review for coreboot: f70d835 WIP: kontron/it8516e: ACPI code drop
by Nico Huber 25 May '13

25 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3287 -gerrit commit f70d835a9561a4812b32fa2299a282b7f8a1ac7d Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu May 23 18:14:36 2013 +0200 WIP: kontron/it8516e: ACPI code drop An example how the ACPI framework can be used. Change-Id: Ifd6765821d9873112ebaae1af28a9dec97c3146e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/ec/kontron/it8516e/acpi/ec.asl | 115 ++++++++++++++++++++++++++++ src/ec/kontron/it8516e/acpi/pm_channels.asl | 115 ++++++++++++++++++++++++++++ 2 files changed, 230 insertions(+) diff --git a/src/ec/kontron/it8516e/acpi/ec.asl b/src/ec/kontron/it8516e/acpi/ec.asl new file mode 100644 index 0000000..bdae967 --- /dev/null +++ b/src/ec/kontron/it8516e/acpi/ec.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8516E in the configuration used by Kontron: + * 2xUART, + * PS/2 Mouse, Keyboard + * Two PM Channels + * + * It allows the change of IO ports, IRQs and DMA settings on the devices + * and disabling and reenabling logical devices. + * + * Controlled by the following preprocessor defines: + * IT8516E_EC_DEV Device identifier for this EC (e.g. EC0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * IT8516E_FIRST_DATA I/o address of the EC_DATA register on the first + * pm channel + * IT8516E_FIRST_SC I/o address of the EC_SC register on the first + * pm channel + * IT8516E_SECOND_DATA I/o address of the EC_DATA register on the second + * pm channel + * IT8516E_SECOND_SC I/o address of the EC_SC register on the second + * pm channel + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8516E +#include <superio/acpi/pnp.asl> + +Device(IT8516E_EC_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Kontron IT8516E Embedded Controller")) + Name (_UID, SUPERIO_UID(IT8516E_EC_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_EXIT_MAGIC_1ST + #include <superio/acpi/pnp_config.asl> + + Method (_PSC) + { + /* No PM: always in C0 */ + Return (0) + } + + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #define SUPERIO_UART_LDN 1 + #include <superio/acpi/pnp_uart.asl> + + #undef SUPERIO_UART_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> + + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 6 + #define SUPERIO_KBC_PS2LDN 5 + #include <superio/acpi/pnp_kbc.asl> + + #include "pm_channels.asl" +} diff --git a/src/ec/kontron/it8516e/acpi/pm_channels.asl b/src/ec/kontron/it8516e/acpi/pm_channels.asl new file mode 100644 index 0000000..f18ac36 --- /dev/null +++ b/src/ec/kontron/it8516e/acpi/pm_channels.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef IT8516E_FIRST_DATA +Device (PM1) { + Name (_HID, EisaId("PNP0C02")) + Name (_STR, Unicode("IT8516E PM Channel 1")) + Name (_UID, SUPERIO_UID(PM, 1)) + + /* + * The EC firmware exposes CPU temperature through ec ram + * on the first PM channel. + */ + + #undef EC_DATA_IO + #define EC_DATA_IO IT8516E_FIRST_DATA + #undef EC_SC_IO + #define EC_SC_IO IT8516E_FIRST_SC + #include <ec/acpi/ec.asl> + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, IT8516E_FIRST_DATA, IT8516E_FIRST_DATA, 0x01, 0x01) + IO (Decode16, IT8516E_FIRST_SC, IT8516E_FIRST_SC, 0x01, 0x01) + }) + } + + /* + * Get CPU temperature from first PM channel (in 10th Kelvin) + */ + Method (CTK) + { + Store (EC_READ (0x52), Local0) + If (And (Local0, EC_ERROR_MASK)) { + Return (0) + } + Multiply (Local0, 10, Local0) /* Convert to 10th °C */ + Return (Add (Local0, 2732)) /* Return as 10th Kelvin */ + } +} +#endif + +#ifdef IT8516E_SECOND_DATA +Device (PM2) { + Name (_HID, EisaId("PNP0C02")) + Name (_STR, Unicode("IT8516E PM Channel 2")) + Name (_UID, SUPERIO_UID(PM, 2)) + + /* + * The EC firmware exposes fan and GPIO control through the + * second PM channel. + */ + + #undef EC_DATA_IO + #define EC_DATA_IO IT8516E_SECOND_DATA + #undef EC_SC_IO + #define EC_SC_IO IT8516E_SECOND_SC + #include <ec/acpi/ec.asl> + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, IT8516E_SECOND_DATA, IT8516E_SECOND_DATA, 0x01, 0x01) + IO (Decode16, IT8516E_SECOND_SC, IT8516E_SECOND_SC, 0x01, 0x01) + }) + } + + /* + * Get CPU temperature from second PM channel (in 10th Kelvin) + */ + Method (CTK) + { + Acquire (EC_MUTEX, 0xffff) + Store (SEND_EC_COMMAND (0x20), Local0) /* GET_CPUTEMP */ + If (And (Local0, EC_ERROR_MASK)) { + Release (EC_MUTEX) + Return (0) + } + Store (RECV_EC_DATA (), Local0) /* Temp low byte in 64th °C */ + If (And (Local0, EC_ERROR_MASK)) { + Release (EC_MUTEX) + Return (0) + } + Store (RECV_EC_DATA (), Local1) /* Temp high byte in 64th °C */ + If (And (Local1, EC_ERROR_MASK)) { + Release (EC_MUTEX) + Return (0) + } + Release (EC_MUTEX) + + Or (ShiftLeft (Local1, 8), Local0, Local0) + Store (Divide (Multiply (Local0, 10), 64), Local0) /* Convert to 10th °C */ + Return (Add (Local0, 2732)) /* Return as 10th Kelvin */ + } +} +#endif

1 0

New patch to review for coreboot: 1dcc6dd WIP: Start ACPI framework for PnP (super i/o) devices
by Nico Huber 25 May '13

25 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3286 -gerrit commit 1dcc6dd56926cc662e4e82d4b207f3c927de1545 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu May 23 18:13:23 2013 +0200 WIP: Start ACPI framework for PnP (super i/o) devices I'm trying to make writing ACPI code for super i/o devices more comfortable. pnp.asl hosts some general cpp macros. The other four files are to be included in dsdt trees. They are controlled by cpp macros which should be defined/undefined before inclusion. Work was inspired by Christoph Grentz' ACPI code for the W83627HF. Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/superio/acpi/pnp.asl | 145 +++++++++++++++++++++++++ src/superio/acpi/pnp_config.asl | 84 +++++++++++++++ src/superio/acpi/pnp_generic.asl | 169 +++++++++++++++++++++++++++++ src/superio/acpi/pnp_kbc.asl | 225 +++++++++++++++++++++++++++++++++++++++ src/superio/acpi/pnp_uart.asl | 134 +++++++++++++++++++++++ 5 files changed, 757 insertions(+) diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl new file mode 100644 index 0000000..ba3882a --- /dev/null +++ b/src/superio/acpi/pnp.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ACPI_PNP_DEFS_ASL +#define SUPERIO_ACPI_PNP_DEFS_ASL + +#define _SUPERIO_ID(name, ldn) name ## ldn +#define SUPERIO_ID(name, ldn) _SUPERIO_ID(name, ldn) + +#define STRINGIFY(x) #x +#define EXPAND_AND_STRINGIFY(x) STRINGIFY(x) +#define SUPERIO_UID(name, ldn) \ + EXPAND_AND_STRINGIFY(SUPERIO_CHIP_NAME-SUPERIO_ID(name, ldn)) +#define SUPERIO_NAME(name) EXPAND_AND_STRINGIFY(SUPERIO_CHIP_NAME name) + +/* Some longer identifiers for readability */ +#define PNP_ADDR_REG ADDR +#define PNP_DATA_REG DATA +#define PNP_LOGICAL_DEVICE LDN +#define PNP_DEVICE_ACTIVE ACTR +#define PNP_IO0_HIGH_BYTE IO0H +#define PNP_IO0_LOW_BYTE IO0L +#define PNP_IO1_HIGH_BYTE IO1H +#define PNP_IO1_LOW_BYTE IO1L +#define PNP_IRQ0 IRQ0 +#define PNP_IRQ1 IRQ1 +#define PNP_DMA0 DMA0 + +#define CONFIG_MODE_MUTEX CMMX +#define ENTER_CONFIG_MODE ENCM +#define EXIT_CONFIG_MODE EXCM +#define SWITCH_LDN SWLD +#define PNP_NO_LDN_CHANGE 0xff + +/* Values for ACPI's _STA method */ +#define DEVICE_NOT_PRESENT 0x00 +#define DEVICE_PRESENT_ACTIVE 0x0f +#define DEVICE_PRESENT_INACTIVE 0x0d + + +/* ================== Generic Method bodies ================= */ + +#define PNP_GENERIC_STA(LDN) \ + ENTER_CONFIG_MODE (LDN)\ + If (PNP_DEVICE_ACTIVE) {\ + Store (DEVICE_PRESENT_ACTIVE, Local0)\ + }\ + Else\ + {\ + Store (DEVICE_PRESENT_INACTIVE, Local0)\ + }\ + EXIT_CONFIG_MODE ()\ + Return (Local0)\ + +#define PNP_GENERIC_DIS(LDN) \ + ENTER_CONFIG_MODE (LDN)\ + Store (Zero, PNP_DEVICE_ACTIVE)\ + EXIT_CONFIG_MODE ()\ + + +/* + * Current power state (returns the chip's state) + */ +#define PNP_DEFAULT_PSC \ + Store(^^_PSC (), Local0)\ + Return (Local0) + +/* + * Current power state (returns the chip's state, if it's in + * power saving mode, 1 if this LDN is in power saving mode, + * 0 else) + * + * PM_REG Identifier of a register which powers down the device + * PM_LDN The logical device number to access the PM_REG + * bit + */ +#define PNP_GENERIC_PSC(PM_REG, PM_LDN) \ + Store(^^_PSC (), Local0)\ + If (Local0) { Return (Local0) }\ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (PM_REG, Local0)\ + EXIT_CONFIG_MODE ()\ + If (Local0) { Return (1) }\ + Else { Return (0) }\ + +/* Disable power saving mode */ +#define PNP_GENERIC_PS0(PM_REG, PM_LDN) \ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (Zero, PM_REG)\ + EXIT_CONFIG_MODE () + +/* Enable power saving mode */ +#define PNP_GENERIC_PS1(PM_REG, PM_LDN) \ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (One, PM_REG)\ + EXIT_CONFIG_MODE () + + +/* ==================== Resource helpers ==================== */ + +#define PNP_READ_IO(IO_FROM, RESOURCE_TEMPLATE, IO_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MIN, IO_TAG##I)\ + CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MAX, IO_TAG##A)\ + Or (ShiftLeft (IO_FROM##_HIGH_BYTE, 8), IO_FROM##_LOW_BYTE, Local0)\ + Store (Local0, IO_TAG##I)\ + Store (Local0, IO_TAG##A) + +#define PNP_READ_IRQ(IRQ_FROM, RESOURCE_TEMPLATE, IRQ_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, IRQ_TAG._INT, IRQ_TAG##W)\ + ShiftLeft (One, IRQ_FROM, IRQ_TAG##W) + +#define PNP_READ_DMA(DMA_FROM, RESOURCE_TEMPLATE, DMA_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, DMA_TAG._DMA, DMA_TAG##W)\ + ShiftLeft (One, DMA_FROM, DMA_TAG##W) + +#define PNP_WRITE_IO(IO_TO, RESOURCE, IO_TAG) \ + CreateWordField (RESOURCE, IO_TAG._MIN, IO_TAG##I)\ + Store (And(IO_TAG##I, 0xff), IO_TO##_LOW_BYTE)\ + Store (ShiftRight(IO_TAG##I, 8), IO_TO##_HIGH_BYTE) + +#define PNP_WRITE_IRQ(IRQ_TO, RESOURCE, IRQ_TAG) \ + CreateWordField (RESOURCE, IRQ_TAG._INT, IRQ_TAG##W)\ + Subtract (FindSetLeftBit (IRQ_TAG##W), 1, IRQ_TO) + +#define PNP_WRITE_DMA(DMA_TO, RESOURCE, DMA_TAG) \ + CreateWordField (RESOURCE, DMA_TAG._DMA, DMA_TAG##W)\ + Subtract (FindSetLeftBit (DMA_TAG##W), 1, DMA_TO) + +#endif diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl new file mode 100644 index 0000000..79dca9f --- /dev/null +++ b/src/superio/acpi/pnp_config.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ======== General PnP configuration functions ======= */ + +/* + * Controlled by the following preprocessor defines: + * PNP_ENTER_MAGIC_1ST If defined, specifies the first magic byte + * used to enter config mode. + * PNP_ENTER_MAGIC_2ND If defined, specifies the second magic byte + * used to enter config mode. + * PNP_ENTER_MAGIC_3RD If defined, specifies the third magic byte + * used to enter config mode. + * PNP_EXIT_MAGIC_1ST If defined, specifies the first magic byte + * used to exit config mode. + */ + + +/* + * Mutex for accesses to the configuration ports (prolog and + * epilog commands are used, so synchronization is useful) + */ +Mutex(CONFIG_MODE_MUTEX, 1) + +/* + * Enter configuration mode (and aquire mutex) + * Method must be run before accesssing the configuration region. + * Parameter is the LDN which should be accessed. Values >= 0xFF mean + * no LDN switch should be done. + */ +Method (ENTER_CONFIG_MODE, 1) +{ + Acquire (CONFIG_MODE_MUTEX, 0xFFFF) +#ifdef PNP_ENTER_MAGIC_1ST + Store (PNP_ENTER_MAGIC_1ST, PNP_ADDR_REG) +#ifdef PNP_ENTER_MAGIC_2ND + Store (PNP_ENTER_MAGIC_2ND, PNP_ADDR_REG) +#ifdef PNP_ENTER_MAGIC_3RD + Store (PNP_ENTER_MAGIC_3RD, PNP_ADDR_REG) +#endif +#endif +#endif + If (LLess(Arg0, PNP_NO_LDN_CHANGE)) { + Store(Arg0, PNP_LOGICAL_DEVICE) + } +} + +/* + * Exit configuration mode (i.e. release mutex) + * Method must be run after accessing the configuration region. + */ +Method (EXIT_CONFIG_MODE) +{ +#ifdef PNP_EXIT_MAGIC_1ST + Store (PNP_EXIT_MAGIC_1ST, PNP_ADDR_REG) +#endif + Release (CONFIG_MODE_MUTEX) +} + +/* + * Just change the LDN. Make sure that you are in config mode (or + * have otherwise acquired CONFIG_MODE_MUTEX), when calling. + */ +Method (SWITCH_LDN, 1) +{ + Store(Arg0, PNP_LOGICAL_DEVICE) +} diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl new file mode 100644 index 0000000..f7a9b13 --- /dev/null +++ b/src/superio/acpi/pnp_generic.asl @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* =================== Generic PnP Device =================== */ + +/* + * Generic setup for PnP devices. + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_PNP_LDN The logical device number on the super i/o + * chip for this device (required) + * SUPERIO_PNP_DDN A string literal that identifies the dos device + * name (DDN) of this device (e.g. "COM1", optional) + * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down + * the logical device (optional) + * SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG + * bit (required if SUPERIO_PNP_PM_REG is defined) + * SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o + * resource (comma seperated, e.g. `0x02, 0x08`, + * optional) + * SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o + * resource (comma seperated, e.g. `0x02, 0x08`, + * optional) + * SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled + * SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled + * SUPERIO_PNP_DMA If defined, the PnP DMA register is enabled + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_PNP_LDN +# error "SUPERIO_PNP_LDN is not defined." +#endif + +Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) { + Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */ + Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN)) + #ifdef SUPERIO_PNP_DDN + Name (_DDN, SUPERIO_PNP_DDN) + #endif + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_PNP_LDN) + } + + Method (_DIS) + { + PNP_GENERIC_DIS(SUPERIO_PNP_LDN) + } + +#ifdef SUPERIO_PNP_PM_REG + Method (_PSC) { + PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } + + Method (_PS0) { + PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } + + Method (_PS1) { + PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } +#else + Method (_PSC) { + PNP_DEFAULT_PSC + } +#endif + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { +#ifdef SUPERIO_PNP_IO0 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + IRQNoFlags (IR0) {} +#endif +#ifdef SUPERIO_PNP_IRQ1 + IRQNoFlags (IR1) {} +#endif +#ifdef SUPERIO_PNP_DMA + DMA (Compatibility, NotBusMaster, Transfer8, DM0) {} +#endif + }) + ENTER_CONFIG_MODE (SUPERIO_PNP_LDN) +#ifdef SUPERIO_PNP_IO0 + PNP_READ_IO(PNP_IO0, CRS, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + PNP_READ_IO(PNP_IO1, CRS, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) +#endif +#ifdef SUPERIO_PNP_IRQ1 + PNP_READ_IRQ(PNP_IRQ1, CRS, IR1) +#endif +#ifdef SUPERIO_PNP_DMA + PNP_READ_DMA(PNP_DMA0, CRS, DM0) +#endif + EXIT_CONFIG_MODE () + Return (CRS) + } + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { +#ifdef SUPERIO_PNP_IO0 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + IRQNoFlags (IR0) {} +#endif +#ifdef SUPERIO_PNP_IRQ1 + IRQNoFlags (IR1) {} +#endif +#ifdef SUPERIO_PNP_DMA + DMA (Compatibility, NotBusMaster, Transfer8, DM0) {} +#endif + }) + ENTER_CONFIG_MODE (SUPERIO_PNP_LDN) +#ifdef SUPERIO_PNP_IO0 + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + PNP_WRITE_IO(PNP_IO1, Arg0, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) +#endif +#ifdef SUPERIO_PNP_IRQ1 + PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1) +#endif +#ifdef SUPERIO_PNP_DMA + PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0) +#endif + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +} diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl new file mode 100644 index 0000000..722ca15 --- /dev/null +++ b/src/superio/acpi/pnp_kbc.asl @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* =================== Keyboard Controller ================== */ + +/* + * Just uses the default i/o ports 0x60/0x64, irq 1 (and 12 for PS/2 + * mouse). Do we have any system that needs this configurable? + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_KBC_LDN The logical device number on the super i/o + * chip for this keyboard controller (required) + * SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in + * the KBC_LDN. Mouse irq is set at IRQ1 of the + * KBC_LDN. + * SUPERIO_KBC_PS2LDN If defined, specifies a second LDN to configure + * PS/2 mouse support. Mouse irq is set at IRQ0 of + * this LDN. + * SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive. + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_KBC_LDN +# error "SUPERIO_KBC_LDN is not defined." +#endif + +#if defined(SUPERIO_KBC_PS2M) && defined(SUPERIO_KBC_PS2LDN) +# error "SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive." +#endif + +Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) { + Name (_HID, EisaId ("PNP0303")) + Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN)) + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_KBC_LDN) + } + + Method (_DIS) + { + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + Store (Zero, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + #if defined(SUPERIO_KBC_PS2LDN) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) + #elif defined(SUPERIO_KBC_PS2M) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1) + #endif + } + + Method (_PSC) { + PNP_DEFAULT_PSC + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IO(PNP_IO1, CRS, IO1) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IO(PNP_IO1, Arg0, IO1) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + #if defined(SUPERIO_KBC_PS2LDN) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) + #elif defined(SUPERIO_KBC_PS2M) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1) + #endif + } +} + +#if defined(SUPERIO_KBC_PS2M) +Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN)) + + Method (_STA) + { + Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ()) + } + + Method (_PSC) { + Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ()) + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_READ_IRQ(PNP_IRQ1, CRS, IR1) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1) + EXIT_CONFIG_MODE () + } +} +#elif defined(SUPERIO_KBC_PS2LDN) +Device (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_PS2LDN)) + + Method (_STA) + { + Store (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA (), Local0) + If (LEqual (Local0, DEVICE_PRESENT_ACTIVE)) { + PNP_GENERIC_STA(SUPERIO_KBC_PS2LDN) + } Else { + Return (Local0) + } + } + + Method (_DIS) + { + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + Store (Zero, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } + + Method (_PSC) { + PNP_DEFAULT_PSC + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR1) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR1) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +} +#endif diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl new file mode 100644 index 0000000..c826106 --- /dev/null +++ b/src/superio/acpi/pnp_uart.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ========================== UART ========================== */ + +/* + * Generic setup for 16550A compatible UARTs. + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_UART_LDN The logical device number on the super i/o + * chip for this UART (required) + * SUPERIO_UART_DDN A string literal that identifies the dos device + * name (DDN) of this uart (e.g. "COM1", optional) + * SUPERIO_UART_PM_REG Identifier of a 1-bit register to power down + * the UART (optional) + * SUPERIO_UART_PM_LDN The logical device number to access the PM_REG + * bit (required if SUPERIO_UART_PM_REG is defined) + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_UART_LDN +# error "SUPERIO_UART_LDN is not defined." +#endif + +Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) + #ifdef SUPERIO_UART_DDN + Name (_DDN, SUPERIO_UART_DDN) + #endif + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_UART_LDN) + } + + Method (_DIS) + { + PNP_GENERIC_DIS(SUPERIO_UART_LDN) + } + +#ifdef SUPERIO_UART_PM_REG + Method (_PSC) { + PNP_GENERIC_PSC(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } + + Method (_PS0) { + PNP_GENERIC_PS0(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } + + Method (_PS1) { + PNP_GENERIC_PS1(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } +#else + Method (_PSC) { + PNP_DEFAULT_PSC + } +#endif + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +}

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New patch to review for coreboot: e934237 ec/acpi: Add ACPI methods for generic EC access
by Nico Huber 25 May '13

25 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3285 -gerrit commit e934237df09f9151e1231f438758a39ead3c54de Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu May 23 16:35:05 2013 +0200 ec/acpi: Add ACPI methods for generic EC access Port most of the functions found in ec/acpi/ec.c to ACPI Source Language (ASL). These functions are used to control embedded controllers with the standard ACPI interface (mostly through i/o ports 0x62 / 0x66). The following methods are implemented and tested against the power managements channels of a ITE IT8516E embedded controller: * WAIT_EC_SC Wait for a bit in the EC_SC register * SEND_EC_COMMAND Send one command byte to the EC_SC register * SEND_EC_DATA Send one data byte to the EC_DATA register * RECV_EC_DATA Read one byte of data from the EC_DATA register * EC_READ Read one byte from ec memory (through cmd 0x80) * EC_WRITE Write one byte to ec memory (through cmd 0x81) To use the provided methods, one should include `ec/acpi/ec.asl` in his EC device code. Prior doing so, two macros should be defined to identify the used i/o ports: * EC_SC_IO I/o address of the EC_SC register * EC_DATA_IO I/o address of the EC_DATA register Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/ec/acpi/ec.asl | 171 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/src/ec/acpi/ec.asl b/src/ec/acpi/ec.asl new file mode 100644 index 0000000..4bc72f7 --- /dev/null +++ b/src/ec/acpi/ec.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * ACPI style embedded controller commands + * + * Controlled by the following preprocessor defines: + * EC_SC_IO I/o address of the EC_SC register + * EC_DATA_IO I/o address of the EC_DATA register + */ + +#define EC_MUTEX ECMX +#define WAIT_EC_SC WECC +#define SEND_EC_COMMAND SECC +#define SEND_EC_DATA SECD +#define RECV_EC_DATA RECD +#define EC_READ ECRD +#define EC_WRITE ECWR +#define EC_SC ECSC +#define EC_DATA ECDT + +#define EC_OBF 0x01 /* Output buffer full (EC_DATA) */ +#define EC_IBF 0x02 /* Input buffer full (EC_DATA or EC_SC) */ + +#define EC_ERROR_MASK 0xff00 +#define EC_TIMEOUT 0x8000 + +#define EC_READ_CMD 0x80 +#define EC_WRITE_CMD 0x81 + +Mutex(EC_MUTEX, 1) + +OperationRegion(ERSC, SystemIO, EC_SC_IO, 1) +Field(ERSC, ByteAcc, NoLock, Preserve) { EC_SC, 8 } +OperationRegion(ERDT, SystemIO, EC_DATA_IO, 1) +Field(ERDT, ByteAcc, NoLock, Preserve) { EC_DATA, 8 } + +/* + * Wait for a bit in the status and command (EC_SC) register + * + * The caller is responsible of acquiring the EC_MUTEX before + * calling this method. + * + * Arg0: Mask, Arg1: State waiting for + * Returns EC_TIMEOUT if timed out, 0 else + */ +Method (WAIT_EC_SC, 2) +{ + Store (0x7ff, Local0) /* Timeout */ + While (LAnd (LNotEqual (And (EC_SC, Arg0), Arg1), Decrement (Local0))) { + Stall (10) + } + If (Local0) { + Return (0) + } Else { + Return (EC_TIMEOUT) + } +} + +/* + * Send command byte in Arg0 to status and command (EC_SC) register + * + * The caller is responsible of acquiring the EC_MUTEX before + * calling this method. + * + * Returns EC_TIMEOUT if timed out, 0 else + */ +Method (SEND_EC_COMMAND, 1) +{ + Store (WAIT_EC_SC (EC_IBF, 0), Local0) + If (LNot (Local0)) { + Store (Arg0, EC_SC) + } + Return (Local0) +} + +/* + * Send data byte in Arg0 to data (EC_DATA) register + * + * The caller is responsible of acquiring the EC_MUTEX before + * calling this method. + * + * Returns EC_TIMEOUT if timed out, 0 else + */ +Method (SEND_EC_DATA, 1) +{ + Store (WAIT_EC_SC (EC_IBF, 0), Local0) + If (LNot (Local0)) { + Store (Arg0, EC_DATA) + } + Return (Local0) +} + +/* + * Read one byte of data from data (EC_DATA) register + * + * The caller is responsible of acquiring the EC_MUTEX before + * calling this method. + * + * Returns EC_TIMEOUT if timed out, the read data byte else + */ +Method (RECV_EC_DATA) +{ + Store (WAIT_EC_SC (EC_OBF, EC_OBF), Local0) + If (LNot (Local0)) { + Return (EC_DATA) + } Else { + Return (Local0) + } +} + +/* + * Read one byte from ec memory (cmd 0x80) + * + * Arg0: Address (1 byte) to read from + * Returns EC_TIMEOUT if timed out, the read data byte else + */ +Method (EC_READ, 1) +{ + Acquire (EC_MUTEX, 0xffff) + Store (SEND_EC_COMMAND (EC_READ_CMD), Local0) + If (LNot (Local0)) { + Store (SEND_EC_DATA (Arg0), Local0) + } + If (LNot (Local0)) { + Store (RECV_EC_DATA (), Local0) + } + Release (EC_MUTEX) + + Return (Local0) +} + +/* + * Write one byte to ec memory (cmd 0x81) + * + * Arg0: Address (1 byte) to write to + * Arg1: Byte to write + * Returns EC_TIMEOUT if timed out, 0 else + */ +Method (EC_WRITE, 2) +{ + Acquire (EC_MUTEX, 0xffff) + Store (SEND_EC_COMMAND (EC_WRITE_CMD), Local0) + If (LNot (Local0)) { + Store (SEND_EC_DATA (Arg0), Local0) + } + If (LNot (Local0)) { + Store (SEND_EC_DATA (Arg1), Local0) + } + Release (EC_MUTEX) + + Return (Local0) +}

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New patch to review for coreboot: 8df9315 southbridge/intel/i82801gx: Add support for CONFIG_SMM_TSEG
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3284 -gerrit commit 8df9315245e823fe32333b6d9642fb484a1ebe9e Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat May 25 13:42:43 2013 +0200 southbridge/intel/i82801gx: Add support for CONFIG_SMM_TSEG Change-Id: I795c112c2432d56681dace5cd1b1d23b1d361c0a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/smi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 5be2404..39570e5 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -29,6 +29,9 @@ #include <cpu/x86/smm.h> #include <string.h> #include "i82801gx.h" +#if CONFIG_NORTHBRIDGE_INTEL_I945 +#include "../../../northbridge/intel/i945/i945.h" +#endif extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_size; @@ -245,7 +248,13 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_SMM_TSEG + pmbase = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD); + pmbase -= CONFIG_I915_UMA_SIZE; + pmbase -= CONFIG_SMM_TSEG_SIZE; +#else pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; +#endif printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN);

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Patch set updated for coreboot: 40a3406 Lenovo ThinkPad X60: Add support for TSEG
by Denis Carikli 25 May '13

25 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3283 -gerrit commit 40a340660c5ca4ceb4e76f5898ba29ec2b6ecec7 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri May 24 14:02:15 2013 +0200 Lenovo ThinkPad X60: Add support for TSEG Change-Id: I9717196e0c524cadff77ba78271cdb6fe627b014 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 737a789..01c006e 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select MARK_GRAPHICS_MEM_WRCOMB + select SMM_TSEG config MAINBOARD_DIR string @@ -55,4 +56,8 @@ config MAX_CPUS int default 2 +config SMM_TSEG_SIZE + hex + default 0x100000 + endif

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coreboot-gerrit May 2013