coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 690c611 Asus F2A85-M: Add IRQ for IOMMU
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3318 -gerrit commit 690c611af6a8162d447ad6cbb6a1329cb764d9d6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 18:45:32 2013 +0200 Asus F2A85-M: Add IRQ for IOMMU Asus F2A85-M Add IRQ for IOMMU. Change-Id: Ic9f02e28aac593cddf7d222a8abb780a10572d32 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/acpi/routing.asl | 11 ++++++++++- src/mainboard/asus/f2a85-m/mptable.c | 6 ++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 03027c3..b939b6a 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -30,6 +30,11 @@ Scope(\_SB) { Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, @@ -84,10 +89,14 @@ Scope(\_SB) { Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ Package(){0x0001FFFF, 0, 0, 17 }, - package(){0x0001FFFF, 1, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ Package(){0x0002FFFF, 0, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 6ed9fca..1760303 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -130,6 +130,12 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

1 0

Patch set updated for coreboot: 940b86e AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3315 -gerrit commit 940b86ecd3534db3b4a07e61a9bec5a526b5b5ae Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:09:44 2013 +0200 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM The IOMMU AGESA needs a reserved scratch space and it wants to allocate the stuff for runtime. So provide a simple allocator for 4 KB CBMEM page. Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + .../amd/agesa/family15tn/fam15tn_callouts.c | 27 ++++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index baec780..efb0f90 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,6 +71,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_NONE 0x00000000 +#define CBMEM_ID_AGESA_RUNTIME 0x41474553 #ifndef __ASSEMBLER__ #include <stdint.h> diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 7031a70..65be67c 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -47,6 +47,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_ROOT, "CBMEM ROOT " }, { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, + { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 59c892f..38bf975 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -26,6 +26,29 @@ #include "cbfs.h" #include "dimmSpd.h" #include "fam15tn_callouts.h" +#include <cbmem.h> + +#define AGESA_RUNTIME_SIZE 4096 + +static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) { + static unsigned int used = 0; + void *p = cbmem_find(CBMEM_ID_AGESA_RUNTIME); + + if ((AGESA_RUNTIME_SIZE - used) < AllocParams->BufferLength) { + return AGESA_BOUNDS_CHK; + } + + /* first time allocation */ + if (!p) { + p = cbmem_add(CBMEM_ID_AGESA_RUNTIME, AGESA_RUNTIME_SIZE); + if (!p) + return AGESA_BOUNDS_CHK; + } + + AllocParams->BufferPointer = p + used; + used += AllocParams->BufferLength; + return AGESA_SUCCESS; +} AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { @@ -48,6 +71,10 @@ AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; + /* if the allocation is for runtime use simple CBMEM data */ + if (Data == HEAP_CALLOUT_RUNTIME) + return alloc_cbmem(AllocParams); + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;

1 0

Patch set updated for coreboot: 1e14a36 AMD Fam15tn: Add IOMMU BAR allocation to northbridge
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3314 -gerrit commit 1e14a3689d14c51a7a7d95c93346ae7b6a49ea97 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:06:43 2013 +0200 AMD Fam15tn: Add IOMMU BAR allocation to northbridge For IOMMU we need to allocate a 512 KB BAR in a non-standard location. Use the standard allocator for that and limit the BAR to 32-bits to be compatible with older systems. Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/device/pci_ids.h | 1 + src/northbridge/amd/agesa/family15tn/Makefile.inc | 1 + src/northbridge/amd/agesa/family15tn/iommu.c | 74 +++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e9e5ab7..b455907 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -287,6 +287,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 #define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index b609ee6..afec3c0 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -20,6 +20,7 @@ romstage-y += fam15tn_callouts.c romstage-y += dimmSpd.c +ramstage-y += iommu.c ramstage-y += northbridge.c ramstage-y += fam15tn_callouts.c ramstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c new file mode 100644 index 0000000..24fc4e3 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x44); + /* Remember this resource has been stored */ + res->flags |= IORESOURCE_STORED; + /* For now, do only 32-bit space allocation */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x44, res->base | (1 << 0)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU, +};

1 0

Patch set updated for coreboot: bf003f9 Asus F2A85-M: Activate IOMMU support
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3317 -gerrit commit bf003f958d64a6da744ebaf3b32f055e0fe5445d Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:12:00 2013 +0200 Asus F2A85-M: Activate IOMMU support Activate the IOMMU support for the Asus F2A85-M. Add the device to `devicetree.cb`. $ pci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] [ 0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS […] [ 0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000 [ 0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600 [ 0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000 […] [ 0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT] [ 0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT] [ 0.598073] pci0000:00: >Requesting ACPI _OSC control (0x1d) [ 0.603808] pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.620508] Freeing initrd memory: 14876k freed […] [ 0.882674] pci 0000:00:01.0: >Boot video device [ 0.882876] PCI: CLS 64 bytes, default 64 [ 0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features: PreF PPR GT IA [ 0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X [ 0.917457] AMD-Vi: Lazy IO/TLB flushing enabled [ 0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff] [ 0.938535] LVT offset 0 assigned for vector 0x400 [ 0.943338] perf: AMD IBS detected (0x000000ff) [ 0.948037] audit: initializing netlink socket (disabled) [ 0.953432] type=2000 audit(1369659616.800:1): initialized [ 0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages […] [ 7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) [ 7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF […] [ 7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X [ 7.885525] radeon 0000:00:01.0: >radeon: using MSI. […] [ 8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010] [ 8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010] [ 8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010] [ 8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010] [ 8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010] [ 8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010] [ 8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010] [ 8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010] [ 8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010] [ 8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010] [ 8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010] [ 8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010] [ 8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010] [ 8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010] [ 8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010] [ 8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010] [ 8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010] [ 8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010] [ 8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010] [ 8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010] [ 8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010] [ 8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010] [ 8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010] [ 8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010] [ 8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010] [ 8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010] [ 8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010] [ 8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010] [ 8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010] [ 8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010] [ 8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010] […] [ 8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010] [ 8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010] [ 8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010] [ 8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010] [ 8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010] [ 8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010] [ 8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010] [ 8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010] [ 8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010] [ 8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010] [ 8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010] [ 8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010] [ 8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010] [ 8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010] [ 8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010] [ 8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010] [ 8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010] [ 8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010] [ 8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010] [ 8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010] [ 8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010] [ 8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010] [ 8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010] [ 8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010] [ 8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010] [ 8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010] [ 8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010] [ 8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010] [ 8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010] [ 8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010] [ 8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010] [ 8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010] [ 8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010] [ 8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 8.963165] radeon 0000:00:01.0: >WB enabled […] It is not known, what the implications of the `IO_PAGE_FAULT` are. Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..4080e8b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -171,7 +171,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..1cc610e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 blue

1 0

Patch set updated for coreboot: 8986276 AMD Fam15tn: Fix IOMMU scratch support in AGESA
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3316 -gerrit commit 898627666ca9a88eb9782c0e3178cf5e0eeb05c6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:00:25 2013 +0200 AMD Fam15tn: Fix IOMMU scratch support in AGESA The IOMMU support is broken and would not even compile otherwise. Just add header file and fix the 64-bit versus 32-bit address issue. Change-Id: I1924a113af12b186edcdf1956cb5ec5453aee34c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 8 ++- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 81 ++++++++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..815ab48 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -203,6 +203,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..3fe0ff0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -78,6 +78,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index b5eb7ed..22d6457 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -84,6 +84,7 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" +#include "GnbIommuScratch.h" #define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S @@ -138,9 +139,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; } + /* align the address to 64 bytes boundary */ +#ifdef __x86_64__ AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; - +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..d300fb6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IOMMU scratch page + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: $ @e \$Date: $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif

1 0

Patch set updated for coreboot: 750ec10 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
by Paul Menzel 27 May '13

27 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3315 -gerrit commit 750ec105fee216e41f9c6d2c031c7e45a4afdfbb Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:09:44 2013 +0200 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM The IOMMU AGESA needs a reserved scratch space and it wants to allocate the stuff for runtime. So provide a simple allocator for 4 KB CBMEM page. Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + .../amd/agesa/family15tn/fam15tn_callouts.c | 27 ++++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index baec780..efb0f90 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,6 +71,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_NONE 0x00000000 +#define CBMEM_ID_AGESA_RUNTIME 0x41474553 #ifndef __ASSEMBLER__ #include <stdint.h> diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 7031a70..65be67c 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -47,6 +47,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_ROOT, "CBMEM ROOT " }, { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, + { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 59c892f..38bf975 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -26,6 +26,29 @@ #include "cbfs.h" #include "dimmSpd.h" #include "fam15tn_callouts.h" +#include <cbmem.h> + +#define AGESA_RUNTIME_SIZE 4096 + +static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) { + static unsigned int used = 0; + void *p = cbmem_find(CBMEM_ID_AGESA_RUNTIME); + + if ((AGESA_RUNTIME_SIZE - used) < AllocParams->BufferLength) { + return AGESA_BOUNDS_CHK; + } + + /* first time allocation */ + if (!p) { + p = cbmem_add(CBMEM_ID_AGESA_RUNTIME, AGESA_RUNTIME_SIZE); + if (!p) + return AGESA_BOUNDS_CHK; + } + + AllocParams->BufferPointer = p + used; + used += AllocParams->BufferLength; + return AGESA_SUCCESS; +} AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { @@ -48,6 +71,10 @@ AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; + /* if the allocation is for runtime use simple CBMEM data */ + if (Data == HEAP_CALLOUT_RUNTIME) + return alloc_cbmem(AllocParams); + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;

1 0

Patch set updated for coreboot: bd395e2 AMD Fam15tn: Add IOMMU BAR allocation to northbridge
by Paul Menzel 27 May '13

27 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3314 -gerrit commit bd395e2d1ca2092355505f42001834c575bf4bad Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:06:43 2013 +0200 AMD Fam15tn: Add IOMMU BAR allocation to northbridge For IOMMU we need to allocate a 512 KB BAR in a non-standard location. Use the standard allocator for that and limit the BAR to 32-bits to be compatible with older systems. Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/device/pci_ids.h | 1 + src/northbridge/amd/agesa/family15tn/Makefile.inc | 1 + src/northbridge/amd/agesa/family15tn/iommu.c | 74 +++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e9e5ab7..b455907 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -287,6 +287,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 #define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index b609ee6..afec3c0 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -20,6 +20,7 @@ romstage-y += fam15tn_callouts.c romstage-y += dimmSpd.c +ramstage-y += iommu.c ramstage-y += northbridge.c ramstage-y += fam15tn_callouts.c ramstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c new file mode 100644 index 0000000..7aeca49 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x44); + /* Remember this resource has been stored */ + res->flags |= IORESOURCE_STORED; + /* For now, do only 32-bit space allocation */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x44, res->base | 1 << 1); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU, +};

1 0

Patch set updated for coreboot: df6975d Asus F2A85-M: Activate IOMMU support
by Paul Menzel 27 May '13

27 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3317 -gerrit commit df6975d55f2e54deaea297c95838d2224e8f6cef Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:12:00 2013 +0200 Asus F2A85-M: Activate IOMMU support Activate the IOMMU support for the Asus F2A85-M. Add the device to `devicetree.cb`. $ pci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] [ 0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS […] [ 0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000 [ 0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600 [ 0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000 […] [ 0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT] [ 0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT] [ 0.598073] pci0000:00: >Requesting ACPI _OSC control (0x1d) [ 0.603808] pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.620508] Freeing initrd memory: 14876k freed […] [ 0.882674] pci 0000:00:01.0: >Boot video device [ 0.882876] PCI: CLS 64 bytes, default 64 [ 0.884867] pci 0000:00:00.2: >can't derive routing for PCI INT A [ 0.890954] pci 0000:00:00.2: >PCI INT A: no GSI [ 0.895556] [ 0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features: PreF PPR GT IA [ 0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X [ 0.917457] AMD-Vi: Lazy IO/TLB flushing enabled [ 0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff] [ 0.938535] LVT offset 0 assigned for vector 0x400 [ 0.943338] perf: AMD IBS detected (0x000000ff) [ 0.948037] audit: initializing netlink socket (disabled) [ 0.953432] type=2000 audit(1369659616.800:1): initialized [ 0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages […] [ 7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) [ 7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF […] [ 7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X [ 7.885525] radeon 0000:00:01.0: >radeon: using MSI. […] [ 8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010] [ 8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010] [ 8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010] [ 8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010] [ 8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010] [ 8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010] [ 8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010] [ 8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010] [ 8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010] [ 8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010] [ 8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010] [ 8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010] [ 8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010] [ 8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010] [ 8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010] [ 8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010] [ 8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010] [ 8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010] [ 8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010] [ 8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010] [ 8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010] [ 8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010] [ 8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010] [ 8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010] [ 8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010] [ 8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010] [ 8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010] [ 8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010] [ 8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010] [ 8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010] [ 8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010] […] [ 8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010] [ 8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010] [ 8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010] [ 8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010] [ 8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010] [ 8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010] [ 8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010] [ 8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010] [ 8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010] [ 8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010] [ 8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010] [ 8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010] [ 8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010] [ 8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010] [ 8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010] [ 8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010] [ 8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010] [ 8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010] [ 8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010] [ 8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010] [ 8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010] [ 8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010] [ 8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010] [ 8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010] [ 8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010] [ 8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010] [ 8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010] [ 8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010] [ 8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010] [ 8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010] [ 8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010] [ 8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010] [ 8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010] [ 8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 8.963165] radeon 0000:00:01.0: >WB enabled […] It is not known, what the implications of the `IO_PAGE_FAULT` are. Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..4080e8b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -171,7 +171,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..1cc610e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 blue

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Patch set updated for coreboot: 5b906ef AMD Fam15tn: Fix IOMMU scratch support in AGESA
by Paul Menzel 27 May '13

27 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3316 -gerrit commit 5b906ef8affd89726a24daf3a3ecae97de2d4767 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:00:25 2013 +0200 AMD Fam15tn: Fix IOMMU scratch support in AGESA The IOMMU support is broken and would not even compile otherwise. Just add header file and fix the 64-bit versus 32-bit address issue. Change-Id: I1924a113af12b186edcdf1956cb5ec5453aee34c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 8 ++- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 81 ++++++++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..815ab48 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -203,6 +203,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..3fe0ff0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -78,6 +78,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index b5eb7ed..22d6457 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -84,6 +84,7 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" +#include "GnbIommuScratch.h" #define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S @@ -138,9 +139,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; } + /* align the address to 64 bytes boundary */ +#ifdef __x86_64__ AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; - +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..d300fb6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IOMMU scratch page + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: $ @e \$Date: $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif

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New patch to review for coreboot: 8258c93 Asus F2A85-M: Activate the IOMMU support
by Rudolf Marek 27 May '13

27 May '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3317 -gerrit commit 8258c93db257065e2c6f59722e80b7e3a4a6bad6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:12:00 2013 +0200 Asus F2A85-M: Activate the IOMMU support Active the IOMMU support for Asus F2A85-M. Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..4080e8b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -171,7 +171,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..1cc610e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 blue

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coreboot-gerrit May 2013