New patch to review for coreboot: 6358465 AMD Geode LX: Add AES PCI device 0:1.2 to `devicetree.cb`
Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3326
-gerrit
commit 6358465ec24f937ec415e0f53400ccc533640694 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Tue May 28 20:59:50 2013 +0200
AMD Geode LX: Add AES PCI device 0:1.2 to `devicetree.cb`
The AMD Geode LX processor features a security block [1], which is exposed as PCI device 0:1.2.
Currently some Geode LX boards in the tree mention it in their `devicetree.cb` and others do not. So add
device pci 1.2 on end # AES
to the boards not having this line to completely describe the devices.
No functionality is changed, as coreboot was able to discover the AES security block anyway.
00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
The following command was used to find all Geode LX `devicetree.cb` files.
$ find src/mainboard -name devicetree.cb | xargs grep -l 'amd/lx'
[1] http://en.wikipedia.org/wiki/AMD_Geode#Geode_LX
Change-Id: Id4565c83ac2c0a3f2994535650bb9f642c0feced Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/mainboard/amd/db800/devicetree.cb | 1 + src/mainboard/amd/norwich/devicetree.cb | 1 + src/mainboard/artecgroup/dbe61/devicetree.cb | 1 + src/mainboard/digitallogic/msm800sev/devicetree.cb | 1 + src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb | 1 + src/mainboard/pcengines/alix1c/devicetree.cb | 1 + src/mainboard/pcengines/alix2d/devicetree.cb | 1 + src/mainboard/traverse/geos/devicetree.cb | 1 + src/mainboard/winent/pl6064/devicetree.cb | 1 + 9 files changed, 9 insertions(+)
diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index 3331a12..db78d7c 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 93effaa..0eba4d7 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb index d270f3d..59e3215 100644 --- a/src/mainboard/artecgroup/dbe61/devicetree.cb +++ b/src/mainboard/artecgroup/dbe61/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 839b767..63377ec 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb index a6dba30..b30c169 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb +++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 85e967a..e33d277 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index d8aa3bc..2b51908 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end device pci 1.1 on end + device pci 1.2 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb index 4a2674e..fbf0bb6 100644 --- a/src/mainboard/traverse/geos/devicetree.cb +++ b/src/mainboard/traverse/geos/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index f900f78..4b88479 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power....
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Paul Menzel