the following patch was just integrated into master:
commit 3cc0d1eb3f611cb7bf0e45d8ccdb0c84f54f54dc
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Mar 26 16:28:21 2013 -0700
exynos5250: assign RAM resources in cpu_init()
This moves the ram resource allocation into cpu_init() so that we
no longer rely on declaring a domain in devicetree.cb (which is kind
of weird for this platform). This does not cause any actual changes
to the coreboot memory table, and paves the way for further updates
to Snow's devicetree.
Change-Id: I141277f59b5d48288f409257bf556a1cfa7a8463
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2923
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed Mar 27 01:15:34 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 27 02:00:51 2013, giving +2
See http://review.coreboot.org/2923 for details.
-gerrit
the following patch was just integrated into master:
commit 6b0d0d6e14f8e385e1457df5699136473144ed60
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Dec 14 17:16:21 2012 -0600
cbfstool: Add update-fit command
Add support for filling in the Firmware Interface Table.
For now it only supports adding microcode entries.
It takes 2 options:
1. Name of file in cbfs where the mircocode is located
2. The number of empty entries in the table.
Verified with go firmware tools. Also commented out updating
microcode in the bootblock. When romstage runs, the CPUs indicate
their microcode is already loaded.
Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2712
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Wed Mar 27 01:03:16 2013, giving +1
See http://review.coreboot.org/2712 for details.
-gerrit
the following patch was just integrated into master:
commit dc7bc8e589c4b9f45e57327c2f989ef8f2a0e7c4
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Mar 26 12:51:36 2013 -0700
cbfstool: Fix cbfs_image.c
- The read-only structures are const now
- cosmetic fixes
- put { on a new line for functions
- move code after structures
Change-Id: Ib9131b80242b91bd5105feaebdf8306a844da1cc
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2922
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Wed Mar 27 00:49:58 2013, giving +1
See http://review.coreboot.org/2922 for details.
-gerrit
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2923
-gerrit
commit f808bf9fd006d97b13e2604e3becfeedec899404
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Mar 26 16:28:21 2013 -0700
exynos5250: assign RAM resources in cpu_init()
This moves the ram resource allocation into cpu_init() so that we
no longer rely on declaring a domain in devicetree.cb (which is kind
of weird for this platform). This does not cause any actual changes
to the coreboot memory table, and paves the way for further updates
to Snow's devicetree.
Change-Id: I141277f59b5d48288f409257bf556a1cfa7a8463
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/cpu/samsung/exynos5250/cpu.c | 29 ++---------------------------
1 file changed, 2 insertions(+), 27 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index bcf4d22..b6eae46 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -4,32 +4,9 @@
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
-static void domain_read_resources(device_t dev)
-{
- ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
-}
-
-static void domain_set_resources(device_t dev)
-{
- assign_resources(dev->link_list);
-}
-
-static unsigned int domain_scan_bus(device_t dev, unsigned int max)
-{
- return max;
-}
-
-
-static struct device_operations domain_ops = {
- .read_resources = domain_read_resources,
- .set_resources = domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = domain_scan_bus,
-};
-
static void cpu_init(device_t dev)
{
+ ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
}
static void cpu_noop(device_t dev)
@@ -47,9 +24,7 @@ static struct device_operations cpu_ops = {
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_ops;
}
}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2921
-gerrit
commit 57f6a3673d5b2e15040d094e79150bf73d292f15
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Mar 26 14:52:04 2013 -0500
chromeos: remote CACHE_ROM automatic selection
It's not appropriate for the chromeos Kconfig to automatically
select CACHE_ROM. The reason is that enabling CACHE_ROM is
dependent on the board and chipset atrributes.
Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index e99e2c8..d5ca212 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -20,7 +20,6 @@ config CHROMEOS
bool
default n
select TPM
- select CACHE_ROM
help
Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported