coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 94d01fb memrange: add 2 new range_entry routines
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2924 -gerrit commit 94d01fbc0b590385f793bfcfb80098515aaef597 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 21:22:42 2013 -0500 memrange: add 2 new range_entry routines Two convenience functions are added to operate on a range_entry: - range_entry_update_tag() - update the entry's tag - memranges_next_entry() - get the next entry after the one provide These functions will be used by a follow on patch to the MTRR code to allow hole punching in WB region when the default MTRR type is UC. Change-Id: I3c2be19c8ea1bbbdf7736c867e4a2aa82df2d611 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 9 +++++++++ src/lib/memrange.c | 10 ++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index 222ce3c..5e14f75 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -62,6 +62,12 @@ static inline unsigned long range_entry_tag(const struct range_entry *r) return r->tag; } +static inline void range_entry_update_tag(struct range_entry *r, + unsigned long new_tag) +{ + r->tag = new_tag; +} + /* Iterate over each entry in a memranges structure. Ranges cannot * be deleted while processing each entry as the list cannot be safely * traversed after such an operation. @@ -105,4 +111,7 @@ void memranges_create_hole(struct memranges *ranges, void memranges_insert(struct memranges *ranges, resource_t base, resource_t size, unsigned long tag); +/* Returns next entry after the provided entry. NULL if r is last. */ +struct range_entry *memranges_next_entry(struct memranges *ranges, + const struct range_entry *r); #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 57637ba..5bc7755 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -304,3 +304,13 @@ void memranges_fill_holes_up_to(struct memranges *ranges, /* Merge all entries that were newly added. */ merge_neighbor_entries(ranges); } + +/* Returns next entry after the provided entry. NULL if r is last. */ +struct range_entry *memranges_next_entry(struct memranges *ranges, + const struct range_entry *r) +{ + if (list_is_last(&r->siblings, &ranges->list)) + return NULL; + + return list_first_entry(&r->siblings, struct range_entry, siblings); +}

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Patch set updated for coreboot: 92e262b haswell: add option to mark graphics memory write-combining.
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2893 -gerrit commit 92e262b7922e3200357ec79ece8b0fc8db490dab Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:23:05 2013 -0500 haswell: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/Kconfig | 8 ++++++++ src/northbridge/intel/haswell/gma.c | 19 ++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f689780..12f865a 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -82,6 +82,14 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE The amount of anticipated stack usage from the data cache during pre-ram rom stage execution. +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index d085066..0a67b6a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -217,12 +217,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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Patch set updated for coreboot: 15835d5 sandybridge: add option to mark graphics memory write-combining.
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2894 -gerrit commit 15835d54e538302beef6e355cc45d81fd7c8b82d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:25:37 2013 -0500 sandybridge: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/sandybridge/Kconfig | 8 ++++++++ src/northbridge/intel/sandybridge/gma.c | 19 ++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 56d2cd7..6c9ae99 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -107,6 +107,14 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..853139e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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Patch set updated for coreboot: feafe3e chromeos: remove CACHE_ROM automatic selection
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2921 -gerrit commit feafe3ea0e659b349d0d72a9427926e165cf850e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:52:04 2013 -0500 chromeos: remove CACHE_ROM automatic selection It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e99e2c8..d5ca212 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

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Patch set updated for coreboot: 712be94 libpayload: add x86 ROM variable MTRR support
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2920 -gerrit commit 712be949b1abd642615b74f9b2255f8de4c247d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:34:37 2013 -0500 libpayload: add x86 ROM variable MTRR support On x86, Coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/x86/coreboot.c | 23 ++++++++++++++++++++++- payloads/libpayload/include/coreboot_tables.h | 12 ++++++++++++ payloads/libpayload/include/sysinfo.h | 5 +++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index f4f9b86..77e094f 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -158,6 +158,14 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif +#if CONFIG_ARCH_X86 +static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) +{ + struct cb_x86_rom_mtrr *rom_mtrr = ptr; + info->x86_rom_var_mtrr_index = index; +} +#endif + static void cb_parse_string(unsigned char *ptr, char **info) { *info = (char *)((struct cb_string *)ptr)->string; @@ -281,6 +289,11 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; +#if CONFIG_ARCH_X86 + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(ptr, info); + break; +#endif } ptr += rec->size; @@ -294,7 +307,15 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + int ret; + +#if CONFIG_ARCH_X86 + /* Ensure the variable range MTRR index covering the ROM is set to + * an invalid value. */ + info->x86_rom_var_mtrr_index = -1; +#endif + + ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); if (ret != 1) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 38bda55..02c9449 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -217,6 +217,18 @@ struct cb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define CB_TAG_X86_ROM_MTRR 0x0021 +struct cb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. If one wants to + * enable caching the ROM, the variable MTRR needs to be set to + * write-protect. To disable the caching after enabling set the + * type to uncacheable. */ + uint32_t index; +}; + + #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e05ef9f..a4afd01 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -99,6 +99,11 @@ struct sysinfo_t { void *vdat_addr; u32 vdat_size; #endif + +#ifdef CONFIG_ARCH_X86 + long x86_rom_var_mtrr_index; +#endif + void *tstamp_table; void *cbmem_cons; void *mrc_cache;

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Patch set updated for coreboot: 2424daf x86: add rom cache variable MTRR index to tables
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2919 -gerrit commit 2424daf4eb57759238a1d59ce72b3f94ae3225b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:09:39 2013 -0500 x86: add rom cache variable MTRR index to tables Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 5 +++++ src/include/boot/coreboot_tables.h | 8 ++++++++ src/include/cpu/x86/mtrr.h | 3 +++ src/lib/coreboot_table.c | 24 ++++++++++++++++++++++++ 4 files changed, 40 insertions(+) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index c847d2c..d8c5da1 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void) #if CONFIG_CACHE_ROM static long rom_cache_mtrr = -1; +long x86_mtrr_rom_cache_var_index(void) +{ + return rom_cache_mtrr; +} + void x86_mtrr_enable_rom_caching(void) { msr_t msr_val; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f624ac1..a7e4ab0 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -250,6 +250,14 @@ struct lb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define LB_TAG_X86_ROM_MTRR 0x0021 +struct lb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. */ + uint32_t index; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bff736d..15a5cad 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -78,9 +78,12 @@ int x86_mtrr_check(void); #if CONFIG_CACHE_ROM void x86_mtrr_enable_rom_caching(void); void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); #else static inline void x86_mtrr_enable_rom_caching(void) {} static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } #endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index b9a82a8..b61f054 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -40,6 +40,9 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#if CONFIG_ARCH_X86 +#include <cpu/x86/mtrr.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -237,6 +240,25 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ + +static void lb_x86_rom_cache(struct lb_header *header) +{ +#if CONFIG_ARCH_X86 + long mtrr_index; + struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; + + mtrr_index = x86_mtrr_rom_cache_var_index(); + + if (mtrr_index < 0) + return; + + lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); + lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; + lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); + lb_x86_rom_mtrr->index = mtrr_index; +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -539,6 +561,8 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); + /* Communicate x86 variable MTRR ROM cache information. */ + lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */

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Patch set updated for coreboot: 5e7f0ca x86: mtrr: add CONFIG_ROM_CACHE support
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2918 -gerrit commit 5e7f0ca99cb1589c50d4a45c77ed4511a2245a55 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 12:47:47 2013 -0500 x86: mtrr: add CONFIG_ROM_CACHE support The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR specifically for setting up write-protect cachine of the ROM. It is assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole area should be cached just under 4GiB. If enabled, the MTRR code will allocate but not enable rom caching. It is up to the callers of the MTRR code to explicitly enable (and disable afterwards) through the use of 2 new functions: - x86_mtrr_enable_rom_caching() - x86_mtrr_disable_rom_caching() Additionally, the CACHE_ROM option is exposed to the config menu so that it is not just selected by the chipset or board. The reasoning is that through a multitude of options CACHE_ROM may not be appropriate for enabling. Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 5 +++- src/cpu/x86/mtrr/mtrr.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 16 +++++++++++++ 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 8f05bf3..6c6a73f 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -56,8 +56,11 @@ config LOGICAL_CPUS default y config CACHE_ROM - bool + bool "Allow for caching system ROM." default n + help + When selected a variable range MTRR is allocated for coreboot and + the bootloader enable caching of the system ROM for faster access. config SMM_TSEG bool diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8bf69c5..c847d2c 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -163,6 +163,16 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); +#if CONFIG_CACHE_ROM + /* Add a write-protect region covering the ROM size + * when CONFIG_CACHE_ROM is enabled. The ROM is assumed + * to be located at 4GiB - rom size. */ + resource_t rom_base = RANGE_TO_PHYS_ADDR( + RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); + memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); +#endif + /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -335,6 +345,44 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } +/* Keep track of the MTRR that covers the ROM for caching purposes. */ +#if CONFIG_CACHE_ROM +static long rom_cache_mtrr = -1; + +void x86_mtrr_enable_rom_caching(void) +{ + msr_t msr_val; + unsigned long index; + + if (rom_cache_mtrr < 0) + return; + + index = rom_cache_mtrr; + disable_cache(); + msr_val = rdmsr(MTRRphysBase_MSR(index)); + msr_val.lo &= ~0xff; + msr_val.lo |= MTRR_TYPE_WRPROT; + wrmsr(MTRRphysBase_MSR(index), msr_val); + enable_cache(); +} + +void x86_mtrr_disable_rom_caching(void) +{ + msr_t msr_val; + unsigned long index; + + if (rom_cache_mtrr < 0) + return; + + index = rom_cache_mtrr; + disable_cache(); + msr_val = rdmsr(MTRRphysBase_MSR(index)); + msr_val.lo &= ~0xff; + wrmsr(MTRRphysBase_MSR(index), msr_val); + enable_cache(); +} +#endif + struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -382,6 +430,17 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; +#if CONFIG_CACHE_ROM + /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing + * one to turn on caching for faster ROM access. However, it is + * left to the MTRR callers to enable it. */ + if (mtrr_type == MTRR_TYPE_WRPROT) { + mtrr_type = MTRR_TYPE_UNCACHEABLE; + if (rom_cache_mtrr < 0) + rom_cache_mtrr = var_state->mtrr_index; + } +#endif + printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 618a93c..bff736d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,6 +52,10 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. + * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling + * the caching of the ROM. However, it is set to uncacheable (UC). It + * is the responsiblity of the caller to enable it by calling + * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -67,6 +71,18 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); +/* ROM caching can be used after variable MTRRs are set up. Beware that + * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on + * one's IO hole size and WRCOMB resources. Be sure to check the console + * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. */ +#if CONFIG_CACHE_ROM +void x86_mtrr_enable_rom_caching(void); +void x86_mtrr_disable_rom_caching(void); +#else +static inline void x86_mtrr_enable_rom_caching(void) {} +static inline void x86_mtrr_disable_rom_caching(void) {} +#endif /* CONFIG_CACHE_ROM */ + #endif #if !defined(CONFIG_RAMTOP)

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Patch set updated for coreboot: fa2c9a6 haswell: add option to mark graphics memory write-combining.
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2893 -gerrit commit fa2c9a6ef2948955e2ac2b9fdb11611ae4c8c677 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:23:05 2013 -0500 haswell: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/Kconfig | 8 ++++++++ src/northbridge/intel/haswell/gma.c | 19 ++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f689780..12f865a 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -82,6 +82,14 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE The amount of anticipated stack usage from the data cache during pre-ram rom stage execution. +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index d085066..0a67b6a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -217,12 +217,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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Patch set updated for coreboot: c9c21dc mtrr: honor IORESOURCE_WRCOMB
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2892 -gerrit commit c9c21dcb0b4a245a9ed57f0ccca3593ede722e98 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:10:34 2013 -0500 mtrr: honor IORESOURCE_WRCOMB All resources that set the IORESOURCE_WRCOMB attribute which are also marked as IORESOURCE_PREFETCH will have a MTRR set up that is of the write-combining cacheable type. The only resources on x86 that can be set to write-combining are prefetchable ones. Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8bcdc6e..8bf69c5 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -142,10 +142,12 @@ static struct memranges *get_physical_address_space(void) * time remove unacheable regions from the cacheable ones. */ if (addr_space == NULL) { struct range_entry *r; - const unsigned long mask = IORESOURCE_CACHEABLE; + unsigned long mask; + unsigned long match; addr_space = &addr_space_storage; + mask = IORESOURCE_CACHEABLE; /* Collect cacheable and uncacheable address ranges. The * uncacheable regions take precedence over the cacheable * regions. */ @@ -153,6 +155,14 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, 0, MTRR_TYPE_UNCACHEABLE); + /* Handle any write combining resources. Only prefetchable + * resources with the IORESOURCE_WRCOMB flag are appropriate + * for this MTRR type. */ + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + mask |= match; + memranges_add_resources(addr_space, mask, match, + MTRR_TYPE_WRCOMB); + /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space.

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Patch set updated for coreboot: 5917619 sandybridge: add option to mark graphics memory write-combining.
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2894 -gerrit commit 59176197e10b3498b5bf99773be183dddb317334 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:25:37 2013 -0500 sandybridge: add option to mark graphics memory write-combining. The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/sandybridge/Kconfig | 8 ++++++++ src/northbridge/intel/sandybridge/gma.c | 19 ++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 56d2cd7..6c9ae99 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -107,6 +107,14 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..853139e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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coreboot-gerrit March 2013