coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

1 participants
443 discussions

Patch set updated for coreboot: e8215a2 x86: add new mtrr implementation
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2889 -gerrit commit e8215a26ba537de520192eae1d6b7aa75be28db7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:09:47 2013 -0500 x86: add new mtrr implementation The old MTRR code had issues using too many variable MTRRs depending on the physical address space layout dictated by the device resources. This new implementation calculates the default MTRR type by comparing the number of variable MTRRs used for each type. This avoids the need for IORESOURE_UMA_FB because in many of those situations setting the default type to WB frees up the variable MTTRs to set that space to UC. Additionally, it removes the need for IORESOURCE_IGNORE_MTRR becuase the new mtrr uses the memrange library which does merging of resources. Lastly, the sandybridge gma has its speedup optimization removed for the graphics memory by writing a pre-determined MTRR index. That will be fixed in an upcoming patch once write-combining support is added to the resources. Slight differences from previous MTRR code: - The number of reserved OS MTRRs is not a hard limit. It's now advisory as PAT can be used by the OS to setup the regions to the caching policy desired. - The memory types are calculated once by the first CPU to run the code. After that all other CPUs use that value. - CONFIG_CACHE_ROM support was dropped. It will be added back in its own change. A pathological case that was previously fixed by changing vendor code to adjust the IO hole location looked like the following: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 As noted by the output below it's impossible to accomodate those ranges even with 10 variable MTRRS. However, because the code can select WB as the default MTRR type it can be done in 6 MTRRs: MTRR: default type WB/UC MTRR counts: 6/14. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 755 +++++++++++++++++--------------- src/include/cpu/x86/mtrr.h | 34 +- src/northbridge/intel/sandybridge/gma.c | 16 +- 3 files changed, 426 insertions(+), 379 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 7076a7e..8bcdc6e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -4,6 +4,7 @@ * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel * * Copyright 2000 Silicon Integrated System Corporation + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,14 +24,9 @@ * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming */ -/* - 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed - 2005.6 Eric add address bit in x86_setup_mtrrs - 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, - for AMD, it will not use x86_setup_fixed_mtrrs -*/ - #include <stddef.h> +#include <stdlib.h> +#include <string.h> #include <console/console.h> #include <device/device.h> #include <cpu/x86/msr.h> @@ -39,6 +35,7 @@ #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <arch/acpi.h> +#include <memrange.h> #if CONFIG_X86_AMD_FIXED_MTRRS #include <cpu/amd/mtrr.h> #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) @@ -46,12 +43,6 @@ #define MTRR_FIXED_WRBACK_BITS 0 #endif -static unsigned int mtrr_msr[] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, - MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, -}; - /* 2 MTRRS are reserved for the operating system */ #define BIOS_MTRRS 6 #define OS_MTRRS 2 @@ -75,79 +66,20 @@ void enable_fixed_mtrr(void) msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0xc00; + msr.lo |= MTRRdefTypeEn | MTRRdefTypeFixEn; wrmsr(MTRRdefType_MSR, msr); } -static void enable_var_mtrr(void) +static void enable_var_mtrr(unsigned char deftype) { msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= MTRRdefTypeEn; + msr.lo &= ~0xff; + msr.lo |= MTRRdefTypeEn | deftype; wrmsr(MTRRdefType_MSR, msr); } -/* setting variable mtrr, comes from linux kernel source */ -void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned address_bits) -{ - msr_t base, mask; - unsigned address_mask_high; - - if (reg >= total_mtrrs) - return; - - // it is recommended that we disable and enable cache when we - // do this. - if (sizek == 0) { - disable_cache(); - - msr_t zero; - zero.lo = zero.hi = 0; - /* The invalid bit is kept in the mask, so we simply clear the - relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); - - enable_cache(); - return; - } - - - address_mask_high = ((1u << (address_bits - 32u)) - 1u); - - base.hi = basek >> 22; - base.lo = basek << 10; - - if (sizek < 4*1024*1024) { - mask.hi = address_mask_high; - mask.lo = ~((sizek << 10) -1); - } - else { - mask.hi = address_mask_high & (~((sizek >> 22) -1)); - mask.lo = 0; - } - - // it is recommended that we disable and enable cache when we - // do this. - disable_cache(); - - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - base.lo |= type; - mask.lo |= MTRRphysMaskValid; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); - - enable_cache(); - - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", - reg, basek >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") - ); -} - /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { @@ -172,343 +104,458 @@ static inline unsigned int fls(unsigned int x) return r; } -/* setting up variable and fixed mtrr - * - * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: - * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). - * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous - * requirement. So a 8K range must be 8K aligned not 4K aligned. - * - * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). - * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). - * A 124MB (128MB - 4MB SMA) example: - * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). - * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. - * - * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, - * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula - * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. - * The same 124MB example: - * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) - * or a 156MB (128MB + 32MB - 4MB SMA) example: - * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) - */ +#define MTRR_VERBOSE_LEVEL BIOS_NEVER + +/* MTRRs are at a 4KiB granularity. Therefore all address calculations can + * be done with 32-bit numbers. This allows for the MTRR code to handle + * up to 2^44 bytes (16 TiB) of address space. */ +#define RANGE_SHIFT 12 +#define ADDR_SHIFT_TO_RANGE_SHIFT(x) \ + (((x) > RANGE_SHIFT) ? ((x) - RANGE_SHIFT) : RANGE_SHIFT) +#define PHYS_TO_RANGE_ADDR(x) ((x) >> RANGE_SHIFT) +#define RANGE_TO_PHYS_ADDR(x) (((resource_t)(x)) << RANGE_SHIFT) +#define NUM_FIXED_MTRRS (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR) + +/* The minimum alignment while handling variable MTRR ranges is 64MiB. */ +#define MTRR_MIN_ALIGN PHYS_TO_RANGE_ADDR(64 << 20) +/* Helpful constants. */ +#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20) +#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) + +static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) +{ + return PHYS_TO_RANGE_ADDR(range_entry_base(r)); +} -static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) +static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) { - unsigned int i; - unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; - msr_t msr; - msr.lo = msr.hi = 0; /* Shut up gcc */ - for(i = first; i < last; i++) { - /* When I switch to a new msr read it in */ - if (fixed_msr != i >> 3) { - /* But first write out the old msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } - fixed_msr = i>>3; - msr = rdmsr(mtrr_msr[fixed_msr]); - } - if ((i & 7) < 4) { - msr.lo &= ~(0xff << ((i&3)*8)); - msr.lo |= type << ((i&3)*8); - } else { - msr.hi &= ~(0xff << ((i&3)*8)); - msr.hi |= type << ((i&3)*8); - } - } - /* Write out the final msr */ - if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { - disable_cache(); - wrmsr(mtrr_msr[fixed_msr], msr); - enable_cache(); - } + return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } -static unsigned fixed_mtrr_index(unsigned long addrk) +static struct memranges *get_physical_address_space(void) { - unsigned index; - index = (addrk - 0) >> 6; - if (index >= 8) { - index = ((addrk - 8*64) >> 4) + 8; + static struct memranges *addr_space; + static struct memranges addr_space_storage; + + /* In order to handle some chipsets not being able to pre-determine + * uncacheable ranges, such as graphics memory, at resource inseration + * time remove unacheable regions from the cacheable ones. */ + if (addr_space == NULL) { + struct range_entry *r; + const unsigned long mask = IORESOURCE_CACHEABLE; + + addr_space = &addr_space_storage; + + /* Collect cacheable and uncacheable address ranges. The + * uncacheable regions take precedence over the cacheable + * regions. */ + memranges_init(addr_space, mask, mask, MTRR_TYPE_WRBACK); + memranges_add_resources(addr_space, mask, 0, + MTRR_TYPE_UNCACHEABLE); + + /* The address space below 4GiB is special. It needs to be + * covered entirly by range entries so that MTRR calculations + * can be properly done for the full 32-bit address space. + * Therefore, ensure holes are filled up to 4GiB as + * uncacheable */ + memranges_fill_holes_up_to(addr_space, + RANGE_TO_PHYS_ADDR(RANGE_4GB), + MTRR_TYPE_UNCACHEABLE); + + printk(BIOS_DEBUG, "MTRR: Physical address space:\n"); + memranges_each_entry(r, addr_space) + printk(BIOS_DEBUG, + "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", + range_entry_base(r), range_entry_end(r), + range_entry_size(r), range_entry_tag(r)); } - if (index >= 24) { - index = ((addrk - (8*64 + 16*16)) >> 2) + 24; - } - if (index > NUM_FIXED_RANGES) { - index = NUM_FIXED_RANGES; - } - return index; + + return addr_space; } -static unsigned int range_to_mtrr(unsigned int reg, - unsigned long range_startk, unsigned long range_sizek, - unsigned long next_range_startk, unsigned char type, - unsigned int address_bits, unsigned int above4gb) +/* Fixed MTRR descriptor. This structure defines the step size and begin + * and end (exclusive) address covered by a set of fixe MTRR MSRs. + * It also describes the offset in byte intervals to store the calculated MTRR + * type in an array. */ +struct fixed_mtrr_desc { + uint32_t begin; + uint32_t end; + uint32_t step; + int range_index; + int msr_index_base; +}; + +/* Shared MTRR calculations. Can be reused by APs. */ +static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; + +/* Fixed MTRR descriptors. */ +static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { + { PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000), + PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRRfix64K_00000_MSR }, + { PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000), + PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRRfix16K_80000_MSR }, + { PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000), + PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRRfix4K_C0000_MSR }, +}; + +static void calc_fixed_mtrrs(void) { - unsigned long hole_startk = 0, hole_sizek = 0; - - if (!range_sizek) { - /* If there's no MTRR hole, this function will bail out - * here when called for the hole. - */ - printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk); - return reg; - } + static int fixed_mtrr_types_initialized; + struct memranges *phys_addr_space; + struct range_entry *r; + const struct fixed_mtrr_desc *desc; + const struct fixed_mtrr_desc *last_desc; + uint32_t begin; + uint32_t end; + int type_index; + + if (fixed_mtrr_types_initialized) + return; - if (reg >= bios_mtrrs) { - printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", - range_startk >>10, range_sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); - return reg; - } + phys_addr_space = get_physical_address_space(); -#define MIN_ALIGN 0x10000 /* 64MB */ - - if (above4gb == 2 && type == MTRR_TYPE_WRBACK && - range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { - /* - * If this range is not divisible then instead - * make a larger range and carve out an uncached hole. - */ - hole_startk = range_startk + range_sizek; - hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); - range_sizek += hole_sizek; - } + /* Set all fixed ranges to uncacheable first. */ + memset(&fixed_mtrr_types[0], MTRR_TYPE_UNCACHEABLE, NUM_FIXED_RANGES); - while(range_sizek) { - unsigned long max_align, align; - unsigned long sizek; - /* Compute the maximum size I can make a range */ - max_align = fls(range_startk); - align = fms(range_sizek); - if (align > max_align) { - align = max_align; - } - sizek = 1 << align; - - /* if range is above 4GB, MTRR is needed - * only if above4gb flag is set - */ - if (range_startk < 0x100000000ull / 1024 || above4gb) - set_var_mtrr(reg++, range_startk, sizek, type, address_bits); - range_startk += sizek; - range_sizek -= sizek; - if (reg >= bios_mtrrs) { - printk(BIOS_ERR, "Running out of variable MTRRs!\n"); + desc = &fixed_mtrr_desc[0]; + last_desc = &fixed_mtrr_desc[ARRAY_SIZE(fixed_mtrr_desc) - 1]; + type_index = desc->range_index; + + memranges_each_entry(r, phys_addr_space) { + begin = range_entry_base_mtrr_addr(r); + end = range_entry_end_mtrr_addr(r); + + if (begin >= last_desc->end) break; + + if (end > last_desc->end) + end = last_desc->end; + + /* Get to the correct fixed mtrr descriptor. */ + while (begin >= desc->end) + desc++; + + type_index = desc->range_index; + type_index += (begin - desc->begin) / desc->step; + + while (begin != end) { + unsigned char type; + + type = range_entry_tag(r); + printk(MTRR_VERBOSE_LEVEL, + "MTRR addr 0x%x-0x%x set to %d type @ %d\n", + begin, begin + desc->step, type, type_index); + if (type == MTRR_TYPE_WRBACK) + type |= MTRR_FIXED_WRBACK_BITS; + fixed_mtrr_types[type_index] = type; + type_index++; + begin += desc->step; + if (begin == desc->end) + desc++; } } + fixed_mtrr_types_initialized = 1; +} + +static void commit_fixed_mtrrs(void) +{ + int i; + int j; + int msr_num; + int type_index; + /* 8 ranges per msr. */ + msr_t fixed_msrs[NUM_FIXED_MTRRS]; + unsigned long msr_index[NUM_FIXED_MTRRS]; + + memset(&fixed_msrs, 0, sizeof(fixed_msrs)); - if (hole_sizek) { - printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", - hole_startk >> 10, (hole_startk + hole_sizek) >> 10); - reg = range_to_mtrr(reg, hole_startk, hole_sizek, - next_range_startk, MTRR_TYPE_UNCACHEABLE, - address_bits, above4gb); + disable_cache(); + + msr_num = 0; + type_index = 0; + for (i = 0; i < ARRAY_SIZE(fixed_mtrr_desc); i++) { + const struct fixed_mtrr_desc *desc; + int num_ranges; + + desc = &fixed_mtrr_desc[i]; + num_ranges = (desc->end - desc->begin) / desc->step; + for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { + msr_index[msr_num] = desc->msr_index_base + + (j / RANGES_PER_FIXED_MTRR); + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 0; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 8; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 16; + fixed_msrs[msr_num].lo |= + fixed_mtrr_types[type_index++] << 24; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 0; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 8; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 16; + fixed_msrs[msr_num].hi |= + fixed_mtrr_types[type_index++] << 24; + msr_num++; + } } - return reg; + for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) { + printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", + msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); + wrmsr(msr_index[i], fixed_msrs[i]); + } + + enable_cache(); } -static unsigned long resk(uint64_t value) +void x86_setup_fixed_mtrrs_no_enable(void) { - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } - else { - resultk = 0xffffffff; - } - return resultk; + calc_fixed_mtrrs(); + commit_fixed_mtrrs(); } -static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) +void x86_setup_fixed_mtrrs(void) { - unsigned int start_mtrr; - unsigned int last_mtrr; - const unsigned char type = MTRR_TYPE_WRBACK | MTRR_FIXED_WRBACK_BITS; - start_mtrr = fixed_mtrr_index(resk(res->base)); - last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); - if (start_mtrr >= NUM_FIXED_RANGES) { - return; - } - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", - start_mtrr, last_mtrr); - set_fixed_mtrrs(start_mtrr, last_mtrr, type); + x86_setup_fixed_mtrrs_no_enable(); + printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); + enable_fixed_mtrr(); } struct var_mtrr_state { - unsigned long range_startk, range_sizek; - unsigned int reg; - unsigned long hole_startk, hole_sizek; - unsigned int address_bits; - unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */ + struct memranges *addr_space; + int above4gb; + int address_bits; + int commit_mtrrs; + int mtrr_index; + int def_mtrr_type; }; -void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) +static void clear_var_mtrr(int index) { - struct var_mtrr_state *state = gp; - unsigned long basek, sizek; - if (state->reg >= bios_mtrrs) - return; + msr_t msr_val; - basek = resk(res->base); - sizek = resk(res->size); + msr_val = rdmsr(MTRRphysMask_MSR(index)); + msr_val.lo &= ~MTRRphysMaskValid; + wrmsr(MTRRphysMask_MSR(index), msr_val); +} - if (res->flags & IORESOURCE_UMA_FB) { - /* FIXME: could I use Write-Combining for Frame Buffer ? */ - state->reg = range_to_mtrr(state->reg, basek, sizek, 0, - MTRR_TYPE_UNCACHEABLE, state->address_bits, state->above4gb); +static void write_var_mtrr(struct var_mtrr_state *var_state, + uint32_t base, uint32_t size, int mtrr_type) +{ + msr_t msr_val; + unsigned long msr_index; + resource_t rbase; + resource_t rsize; + resource_t mask; + + /* Some variable MTRRs are attempted to be saved for the OS use. + * However, it's more important to try to map the full address space + * properly. */ + if (var_state->mtrr_index >= bios_mtrrs) + printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); + if (var_state->mtrr_index >= total_mtrrs) { + printk(BIOS_ERR, "ERROR: Not enough MTTRs available!\n"); return; } - if (res->flags & IORESOURCE_IGNORE_MTRR) { - return; - } + rbase = base; + rsize = size; - if (!(res->flags & IORESOURCE_CACHEABLE)) - return; + rbase = RANGE_TO_PHYS_ADDR(rbase); + rsize = RANGE_TO_PHYS_ADDR(rsize); + rsize = -rsize; - /* See if I can merge with the last range - * Either I am below 1M and the fixed mtrrs handle it, or - * the ranges touch. - */ - if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { - unsigned long endk = basek + sizek; - state->range_sizek = endk - state->range_startk; - return; - } - /* Write the range mtrrs */ - if (state->range_sizek != 0) { - if (state->hole_sizek == 0 && state->above4gb != 2) { - /* We need to put that on to hole */ - unsigned long endk = basek + sizek; - state->hole_startk = state->range_startk + state->range_sizek; - state->hole_sizek = basek - state->hole_startk; - state->range_sizek = endk - state->range_startk; - return; - } - state->reg = range_to_mtrr(state->reg, state->range_startk, - state->range_sizek, basek, MTRR_TYPE_WRBACK, - state->address_bits, state->above4gb); - - state->reg = range_to_mtrr(state->reg, state->hole_startk, - state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, - state->address_bits, state->above4gb); - - state->range_startk = 0; - state->range_sizek = 0; - state->hole_startk = 0; - state->hole_sizek = 0; - } - /* Allocate an msr */ - printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); - state->range_startk = basek; - state->range_sizek = sizek; + mask = (1ULL << var_state->address_bits) - 1; + rsize = rsize & mask; + + printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", + var_state->mtrr_index, rbase, rsize, mtrr_type); + + msr_val.lo = rbase; + msr_val.lo |= mtrr_type; + + msr_val.hi = rbase >> 32; + msr_index = MTRRphysBase_MSR(var_state->mtrr_index); + wrmsr(msr_index, msr_val); + + msr_val.lo = rsize; + msr_val.lo |= MTRRphysMaskValid; + msr_val.hi = rsize >> 32; + msr_index = MTRRphysMask_MSR(var_state->mtrr_index); + wrmsr(msr_index, msr_val); } -void x86_setup_fixed_mtrrs_no_enable(void) +static void calc_var_mtrr_range(struct var_mtrr_state *var_state, + uint32_t base, uint32_t size, int mtrr_type) { - /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again - * and clear out the mtrrs. - */ - - printk(BIOS_DEBUG, "\n"); - /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", - 0, NUM_FIXED_RANGES); - set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); - - /* Now see which of the fixed mtrrs cover ram. - */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_fixed_mtrr_resource, NULL); - printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); + while (size != 0) { + uint32_t addr_lsb; + uint32_t size_msb; + uint32_t mtrr_size; + + addr_lsb = fls(base); + size_msb = fms(size); + + /* All MTRR entries need to have their base aligned to the mask + * size. The maximum size is calculated by a function of the + * min base bit set and maximum size bit set. */ + if (addr_lsb > size_msb) + mtrr_size = 1 << size_msb; + else + mtrr_size = 1 << addr_lsb; + + if (var_state->commit_mtrrs) + write_var_mtrr(var_state, base, mtrr_size, mtrr_type); + + size -= mtrr_size; + base += mtrr_size; + var_state->mtrr_index++; + } } -void x86_setup_fixed_mtrrs(void) +static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state) { - x86_setup_fixed_mtrrs_no_enable(); + struct range_entry *r; + + /* + * For each range that meets the non-default type process it in the + * following manner: + * +------------------+ c2 = end + * | 0 or more bytes | + * +------------------+ b2 = c1 = round_down(end) + * | | + * +------------------+ b1 = a2 = round_up(begin) + * | 0 or more bytes | + * +------------------+ a1 = begin + * + * Thus, there are 3 sub-ranges to configure variable MTRRs for. + */ + memranges_each_entry(r, var_state->addr_space) { + uint32_t a1, a2, b1, b2, c1, c2; + int mtrr_type = range_entry_tag(r); + + /* Skip default type. */ + if (var_state->def_mtrr_type == mtrr_type) + continue; + + a1 = range_entry_base_mtrr_addr(r); + c2 = range_entry_end_mtrr_addr(r); + + /* The end address is under 1MiB. The fixed MTRRs take + * precedence over the variable ones. Therefore this range + * can be ignored. */ + if (c2 < RANGE_1MB) + continue; + + /* Again, the fixed MTRRs take precedence so the beginning + * of the range can be set to 0 if it starts below 1MiB. */ + if (a1 < RANGE_1MB) + a1 = 0; + + /* If the range starts above 4GiB the processing is done. */ + if (!var_state->above4gb && a1 >= RANGE_4GB) + break; - printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); - enable_fixed_mtrr(); -} + /* Clip the upper address to 4GiB if addresses above 4GiB + * are not being processed. */ + if (!var_state->above4gb && c2 > RANGE_4GB) + c2 = RANGE_4GB; + /* Don't align up or down on the range if it is smaller + * than the minimum granularity. */ + if ((c2 - a1) < MTRR_MIN_ALIGN) { + calc_var_mtrr_range(var_state, a1, c2 - a1, mtrr_type); + continue; + } -void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) -/* this routine needs to know how many address bits a given processor - * supports. CPUs get grumpy when you set too many bits in - * their mtrr registers :( I would generically call cpuid here - * and find out how many physically supported but some cpus are - * buggy, and report more bits then they actually support. - * If above4gb flag is set, variable MTRR ranges must be used to - * set cacheability of DRAM above 4GB. If above4gb flag is clear, - * some other mechanism is controlling cacheability of DRAM above 4GB. - */ + b1 = a2 = round_up(a1, MTRR_MIN_ALIGN); + b2 = c1 = round_down(c2, MTRR_MIN_ALIGN); + + calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type); + calc_var_mtrr_range(var_state, b1, b2 - b1, mtrr_type); + calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); + } +} + +static int calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits) { - /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again - * and clear out the mtrrs. - */ + int wb_deftype_count; + int uc_deftype_count; struct var_mtrr_state var_state; - /* Cache as many memory areas as possible */ - /* FIXME is there an algorithm for computing the optimal set of mtrrs? - * In some cases it is definitely possible to do better. - */ - var_state.range_startk = 0; - var_state.range_sizek = 0; - var_state.hole_startk = 0; - var_state.hole_sizek = 0; - var_state.reg = 0; - var_state.address_bits = address_bits; + /* The default MTRR cacheability type is determined by calculating + * the number of MTTRs required for each MTTR type as if it was the + * default. */ + var_state.addr_space = addr_space; var_state.above4gb = above4gb; + var_state.address_bits = address_bits; + var_state.commit_mtrrs = 0; - /* Detect number of variable MTRRs */ - if (above4gb == 2) - detect_var_mtrrs(); - - search_global_resources(IORESOURCE_MEM, IORESOURCE_MEM, - set_var_mtrr_resource, &var_state); + var_state.mtrr_index = 0; + var_state.def_mtrr_type = MTRR_TYPE_WRBACK; + setup_var_mtrrs_by_state(&var_state); + wb_deftype_count = var_state.mtrr_index; - /* Write the last range */ - var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, - var_state.range_sizek, 0, MTRR_TYPE_WRBACK, - var_state.address_bits, var_state.above4gb); + var_state.mtrr_index = 0; + var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE; + setup_var_mtrrs_by_state(&var_state); + uc_deftype_count = var_state.mtrr_index; - var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, - var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, - var_state.address_bits, var_state.above4gb); + printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", + wb_deftype_count, uc_deftype_count); - printk(BIOS_DEBUG, "DONE variable MTRRs\n"); - printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); - /* Clear out the extra MTRR's */ - while(var_state.reg < total_mtrrs) { - set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); + if (wb_deftype_count < uc_deftype_count) { + printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); + return MTRR_TYPE_WRBACK; } + printk(BIOS_DEBUG, "MTRR: UC selected as default type.\n"); + return MTRR_TYPE_UNCACHEABLE; +} -#if CONFIG_CACHE_ROM - /* Enable Caching and speculative Reads for the - * complete ROM now that we actually have RAM. - */ - if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, - MTRR_TYPE_WRPROT, address_bits); +static void commit_var_mtrrs(struct memranges *addr_space, int def_type, + int above4gb, int address_bits) +{ + struct var_mtrr_state var_state; + int i; + + var_state.addr_space = addr_space; + var_state.above4gb = above4gb; + var_state.address_bits = address_bits; + /* Write the MSRs. */ + var_state.commit_mtrrs = 1; + var_state.mtrr_index = 0; + var_state.def_mtrr_type = def_type; + setup_var_mtrrs_by_state(&var_state); + + /* Clear all remaining variable MTTRs. */ + for (i = var_state.mtrr_index; i < total_mtrrs; i++) + clear_var_mtrr(i); +} + +void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) +{ + static int mtrr_default_type = -1; + struct memranges *addr_space; + + addr_space = get_physical_address_space(); + + if (mtrr_default_type == -1) { + if (above4gb == 2) + detect_var_mtrrs(); + mtrr_default_type = + calc_var_mtrrs(addr_space, !!above4gb, address_bits); } -#endif - printk(BIOS_SPEW, "call enable_var_mtrr()\n"); - enable_var_mtrr(); - printk(BIOS_SPEW, "Leave %s\n", __func__); - post_code(0x6A); + disable_cache(); + commit_var_mtrrs(addr_space, mtrr_default_type, !!above4gb, + address_bits); + enable_var_mtrr(mtrr_default_type); + enable_cache(); } void x86_setup_mtrrs(void) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index fe85ad0..618a93c 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -26,6 +26,7 @@ #define MTRRphysMaskValid (1 << 11) #define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258 #define MTRRfix16K_A0000_MSR 0x259 @@ -39,22 +40,33 @@ #define MTRRfix4K_F8000_MSR 0x26f #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) -#include <device/device.h> -/* You should almost NEVER use this function. - * N.B. We worked on a lot of ways to make this continue as static, - * but just making it available ended up being the simplest solution. + +/* + * The MTRR code has some side effects that the callers should be aware for. + * 1. The call sequence matters. x86_setup_mtrrs() calls + * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent + * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers + * want to call the components of x86_setup_mtrrs() because of other + * rquirements the ordering should still preserved. + * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because + * of the nature of the global MTRR enable flag. Therefore, all direct + * or indirect callers of enable_fixed_mtrr() should ensure that the + * variable MTRR MSRs do not contain bad ranges. */ -void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned address_bits); -void enable_fixed_mtrr(void); -void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); -int x86_mtrr_check(void); -void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); +/* + * x86_setup_var_mtrrs() parameters: + * address_bits - number of physical address bits supported by cpu + * above4gb - 2 means dynamically detect number of variable MTRRs available. + * non-zero means handle memory ranges above 4GiB. + * 0 means ignore memory ranges above 4GiB + */ +void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); +void enable_fixed_mtrr(void); void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); +int x86_mtrr_check(void); #endif #if !defined(CONFIG_RAMTOP) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 4a043eb..b9a07a2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -622,25 +622,12 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; - u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Set up an MTRR for the graphics memory BAR to vastly improve - * speed of VGA initialization (and later access). To stay out of - * the way of the MTRR init code, we are using MTRR #8 to cover - * that range. - */ - graphics_base = dev->resource_list[1].base; - graphics_size = dev->resource_list[1].size; - printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n", - graphics_base, graphics_size / 1024); - set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10, - MTRR_TYPE_WRCOMB, 0x24); - /* Init graphics power management */ gma_pm_init_pre_vbios(dev); @@ -655,10 +642,11 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, physbase; + u32 iobase, mmiobase, physbase, graphics_base; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); i915lightup(physbase, iobase, mmiobase, graphics_base);

1 0

Patch set updated for coreboot: 81a30d2 lib: add memrange infrastructure
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2888 -gerrit commit 81a30d2a9712da39c627d573101e3dac89191eb2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 20:44:46 2013 -0500 lib: add memrange infrastructure The memrange infrastructure allows for keeping track of the machine's physical address space. Each memory_range entry in a memory_ranges structure can be tagged with an arbitrary value. It supports merging and deleting ranges as well as filling in holes in the address space with a particular tag. The memrange infrastructure will serve as a shared implementation for address tracking by the MTRR and coreboot mem table code. Change-Id: Id5bea9d2a419114fca55c59af0fdca063551110e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 108 +++++++++++++++++ src/lib/Makefile.inc | 1 + src/lib/memrange.c | 306 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 415 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h new file mode 100644 index 0000000..222ce3c --- /dev/null +++ b/src/include/memrange.h @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef MEMRANGE_H_ +#define MEMRANGE_H_ + +#include <device/resource.h> +#include <list.h> + +/* A memranges structure consists of a list of range_entry(s). The structure + * is exposed so that a memranges can be used on the stack if needed. */ +struct memranges { + struct list_head list; +}; + +/* Each region within a memranges structure is represented by a + * range_entry structure. Use the associated range_entry_(base|end|size|tag) + * functions to interrogate its properties. i.e. don't rely on one's own + * interpretation of the fields. */ +struct range_entry { + resource_t begin; + resource_t end; + struct list_head siblings; + unsigned long tag; +}; + +/* Return inclusive base address of memory range. */ +static inline resource_t range_entry_base(const struct range_entry *r) +{ + return r->begin; +} + +/* Return exclusive end address of memory range. */ +static inline resource_t range_entry_end(const struct range_entry *r) +{ + return r->end + 1; +} + +/* Return size of of memory range. */ +static inline resource_t range_entry_size(const struct range_entry *r) +{ + return r->end - r->begin + 1; +} + +static inline unsigned long range_entry_tag(const struct range_entry *r) +{ + return r->tag; +} + +/* Iterate over each entry in a memranges structure. Ranges cannot + * be deleted while processing each entry as the list cannot be safely + * traversed after such an operation. + * r - range_entry pointer. + * ranges - memranges pointer */ +#define memranges_each_entry(r, ranges) \ + list_for_each_entry(r, &(ranges)->list, siblings) + +/* Initialize and fill a memranges structure according to the + * mask and match type for all memory resources. Tag each entry with the + * specified type. */ +void memranges_init(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag); + +/* Remove and free all entries within the memranges structure. */ +void memranges_teardown(struct memranges *ranges); + +/* Add memory resources that match with the corresponding mask and match. + * Each entry will be tagged with the provided tag. e.g. To populate + * all cacheable memory resources in the range: + * memranges_add_resources(range, IORESOURCE_CACHEABLE, + * IORESROUCE_CACHEABLE, my_cacheable_tag); */ +void memranges_add_resources(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag); + +/* Fill all address ranges up to limit (exclusive) not covered by an entry by + * inserting new entries with the provided tag. */ +void memranges_fill_holes_up_to(struct memranges *ranges, + resource_t limit, unsigned long tag); + +/* Create a hole in the range by deleting/modifying entries that overlap with + * the region specified by base and size. */ +void memranges_create_hole(struct memranges *ranges, + resource_t base, resource_t size); + +/* Insert a resource to the given memranges. All existing ranges + * covered by range specified by base and size will be removed before a + * new one is added. */ +void memranges_insert(struct memranges *ranges, + resource_t base, resource_t size, unsigned long tag); + +#endif /* MEMRANGE_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 02c42a8..9d3588e 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c +ramstage-y += memrange.c # The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. ifeq ($(CONFIG_DYNAMIC_CBMEM),y) diff --git a/src/lib/memrange.c b/src/lib/memrange.c new file mode 100644 index 0000000..57637ba --- /dev/null +++ b/src/lib/memrange.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdlib.h> +#include <console/console.h> +#include <memrange.h> + +/* Coreboot doesn't have a free() function. Therefore, keep a cache of + * free'd entries. */ +static LIST_HEAD(free_list); + +static inline void range_entry_unlink(struct range_entry *r) +{ + list_del_init(&r->siblings); +} + +static struct range_entry *alloc_range(void) +{ + if (!list_empty(&free_list)) { + struct range_entry *r; + + r = list_first_entry(&free_list, struct range_entry, siblings); + range_entry_unlink(r); + return r; + } + return malloc(sizeof(struct range_entry)); +} + +static void range_entry_free(struct range_entry *e) +{ + if (!list_empty(&e->siblings)) + printk(BIOS_ERR, "Freeing linked range_entry!\n"); + list_add(&free_list, &e->siblings); +} + +static inline struct range_entry * +range_list_add(struct list_head *head, resource_t begin, resource_t end, + unsigned long tag) +{ + struct range_entry *new_entry; + + new_entry = alloc_range(); + if (new_entry == NULL) { + printk(BIOS_ERR, "Could not allocate range_entry!\n"); + return NULL; + } + new_entry->begin = begin; + new_entry->end = end; + new_entry->tag = tag; + list_add(&new_entry->siblings, head); + + return new_entry; +} + +static void merge_neighbor_entries(struct memranges *ranges) +{ + struct range_entry *cur; + struct range_entry *prev; + struct range_entry *tmp; + + prev = NULL; + /* Merge all neighbors and delete/free the leftover entry. */ + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + /* First entry. Just set prev. */ + if (prev == NULL) { + prev = cur; + continue; + } + + /* If the previous entry merges with the current update the + * previous entry to cover full range and delete current from + * the list. */ + if (prev->end + 1 >= cur->begin && prev->tag == cur->tag) { + prev->end = cur->end; + range_entry_unlink(cur); + range_entry_free(cur); + continue; + } + + prev = cur; + } +} + +static void remove_memranges(struct memranges *ranges, + resource_t begin, resource_t end, + unsigned long unused) +{ + struct range_entry *cur; + struct range_entry *tmp; + + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + resource_t tmp_end; + + /* No other ranges are affected. */ + if (end < cur->begin) + break; + + /* The removal range starts after this one. */ + if (begin > cur->end) + continue; + + /* The removal range overlaps with the current entry either + * partially or fully. However, we need to adjust the removal + * range for any holes. */ + if (begin <= cur->begin) { + begin = cur->begin; + + /* Full removal. */ + if (end >= cur->end) { + begin = cur->end + 1; + range_entry_unlink(cur); + range_entry_free(cur); + continue; + } + } + + /* Clip the end fragment to do proper splitting. */ + tmp_end = end; + if (end > cur->end) + tmp_end = cur->end; + + /* Hole punched in middle of entry. */ + if (begin > cur->begin && tmp_end < cur->end) { + range_list_add(&cur->siblings, end + 1, cur->end, + cur->tag); + cur->end = begin - 1; + continue; + } + + /* Removal at beginning. */ + if (begin == cur->begin) + cur->begin = tmp_end + 1; + + /* Removal at end. */ + if (tmp_end == cur->end) + cur->end = begin - 1; + } +} + +static void merge_add_memranges(struct memranges *ranges, + resource_t begin, resource_t end, + unsigned long tag) +{ + struct range_entry *cur; + struct list_head *head; + + head = &ranges->list; + + /* Remove all existing entries covered by the range. */ + remove_memranges(ranges, begin, end, -1); + + /* Find the entry to place the new entry after. Since + * remove_memranges() was called above there is a guranteed + * spot for this new entry. */ + list_for_each_entry(cur, &ranges->list, siblings) { + /* Found insertion spot before current entry. */ + if (end < cur->begin) + break; + + /* Keep track of previous entry to insert new entry after it. */ + head = &cur->siblings; + + /* The new entry starts after this one. */ + if (begin > cur->end) + continue; + + } + + /* Add new entry and merge with neighbors. */ + range_list_add(head, begin, end, tag); + merge_neighbor_entries(ranges); +} + +typedef void (*range_action_t)(struct memranges *ranges, + resource_t begin, resource_t end, + unsigned long tag); + +static void do_action(struct memranges *ranges, + resource_t base, resource_t size, unsigned long tag, + range_action_t action) +{ + resource_t end; + resource_t begin; + + /* The addresses are aligned to 4096 bytes: the begin address is + * aligned down while the end address is aligned up to be conservative + * about the full range covered. */ + begin = round_down(base, 4096); + end = begin + size + (base - begin); + end = round_up(end, 4096) - 1; + action(ranges, begin, end, tag); +} + +void memranges_create_hole(struct memranges *ranges, + resource_t base, resource_t size) +{ + do_action(ranges, base, size, -1, remove_memranges); +} + +void memranges_insert(struct memranges *ranges, + resource_t base, resource_t size, unsigned long tag) +{ + do_action(ranges, base, size, tag, merge_add_memranges); +} + +struct collect_context { + struct memranges *ranges; + unsigned long tag; +}; + +static void collect_ranges(void *gp, struct device *dev, struct resource *res) +{ + struct collect_context *ctx = gp; + + memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); +} + +void memranges_add_resources(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + struct collect_context context; + + /* Only deal with MEM resources. */ + mask |= IORESOURCE_MEM; + match |= IORESOURCE_MEM; + + context.ranges = ranges; + context.tag = tag; + search_global_resources(mask, match, collect_ranges, &context); +} + +void memranges_init(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + INIT_LIST_HEAD(&ranges->list); + + memranges_add_resources(ranges, mask, match, tag); +} + +void memranges_teardown(struct memranges *ranges) +{ + struct range_entry *cur; + struct range_entry *tmp; + + /* Merge all neighbors and delete/free the leftover entry. */ + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + range_entry_unlink(cur); + range_entry_free(cur); + } +} + +void memranges_fill_holes_up_to(struct memranges *ranges, + resource_t limit, unsigned long tag) +{ + struct range_entry *cur; + struct range_entry *prev; + struct range_entry *tmp; + + prev = NULL; + list_for_each_entry_safe(cur, tmp, &ranges->list, siblings) { + /* First entry. Just set prev. */ + if (prev == NULL) { + prev = cur; + continue; + } + + /* If the previous entry does not directly preceed the current + * entry then add a new entry just after the previous one. */ + if (range_entry_end(prev) != cur->begin) + range_list_add(&prev->siblings, range_entry_end(prev), + cur->begin - 1, tag); + + prev = cur; + + /* Hit the requested range limit. No other entries after this + * are affected. */ + if (cur->begin >= limit) + break; + } + + /* Handle the case where the limit was never reached. A new entry needs + * to be added to cover the range up to the limit. */ + if (prev != NULL && range_entry_end(prev) < limit) + range_list_add(&prev->siblings, range_entry_end(prev), + limit - 1, tag); + + /* Merge all entries that were newly added. */ + merge_neighbor_entries(ranges); +}

1 0

Patch set updated for coreboot: 461a5a9 chromeos: remove CACHE_ROM automatic selection
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2921 -gerrit commit 461a5a9f79d9df3c00fe07f17fc743acb88682f2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 14:52:04 2013 -0500 chromeos: remove CACHE_ROM automatic selection It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e99e2c8..d5ca212 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

1 0

Patch set updated for coreboot: bc210a1 resources: introduce IORESOURCE_WRCOMB
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2891 -gerrit commit bc210a18b08fe3e3118b1320ba9c9df462c2a031 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:16:58 2013 -0500 resources: introduce IORESOURCE_WRCOMB Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/device/resource.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 6b66605..4bd9698 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ - +#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */

1 0

Patch set updated for coreboot: d5666fb libpayload: add x86 ROM variable MTRR support
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2920 -gerrit commit d5666fb3b0ee5e8addc621019faa3a3c826898cb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:34:37 2013 -0500 libpayload: add x86 ROM variable MTRR support On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/x86/coreboot.c | 21 ++++++++- payloads/libpayload/configs/config.fox | 68 +++++++++++++++++++++++++++ payloads/libpayload/include/coreboot_tables.h | 12 +++++ payloads/libpayload/include/sysinfo.h | 5 ++ 4 files changed, 105 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index f4f9b86..03567d9 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -158,6 +158,12 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif +static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) +{ + struct cb_x86_rom_mtrr *rom_mtrr = ptr; + info->x86_rom_var_mtrr_index = rom_mtrr->index; +} + static void cb_parse_string(unsigned char *ptr, char **info) { *info = (char *)((struct cb_string *)ptr)->string; @@ -281,6 +287,11 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; +#if CONFIG_ARCH_X86 + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(ptr, info); + break; +#endif } ptr += rec->size; @@ -294,7 +305,15 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + int ret; + +#if CONFIG_ARCH_X86 + /* Ensure the variable range MTRR index covering the ROM is set to + * an invalid value. */ + info->x86_rom_var_mtrr_index = -1; +#endif + + ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); if (ret != 1) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); diff --git a/payloads/libpayload/configs/config.fox b/payloads/libpayload/configs/config.fox new file mode 100644 index 0000000..a5d6087 --- /dev/null +++ b/payloads/libpayload/configs/config.fox @@ -0,0 +1,68 @@ +# +# Automatically generated make config: don't edit +# libpayload version: 0.2.0 +# Tue Sep 4 17:53:34 2012 +# + +# +# Generic Options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set +# CONFIG_DEVELOPER is not set +CONFIG_CHROMEOS=y + +# +# Architecture Options +# +CONFIG_ARCH_X86=y +# CONFIG_ARCH_POWERPC is not set +# CONFIG_ARCH_ARMV7 is not set +# CONFIG_MEMMAP_RAM_ONLY is not set +# CONFIG_MULTIBOOT is not set + +# +# Standard Libraries +# +CONFIG_LIBC=y +# CONFIG_CURSES is not set +# CONFIG_TINYCURSES is not set +# CONFIG_PDCURSES is not set +CONFIG_CBFS=y +CONFIG_LZMA=y + +# +# Console Options +# +CONFIG_SKIP_CONSOLE_INIT=y +CONFIG_CBMEM_CONSOLE=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SERIAL_IOBASE=0x3f8 +# CONFIG_SERIAL_SET_SPEED is not set +# CONFIG_SERIAL_ACS_FALLBACK is not set +CONFIG_VIDEO_CONSOLE=y +# CONFIG_VGA_VIDEO_CONSOLE is not set +# CONFIG_GEODELX_VIDEO_CONSOLE is not set +CONFIG_COREBOOT_VIDEO_CONSOLE=y +CONFIG_PC_KEYBOARD=y +CONFIG_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set + +# +# Drivers +# +CONFIG_PCI=y +CONFIG_NVRAM=y +# CONFIG_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_SPEAKER is not set +# CONFIG_STORAGE is not set +CONFIG_USB=y +CONFIG_USB_UHCI=y +CONFIG_USB_OHCI=y +CONFIG_USB_EHCI=y +CONFIG_USB_XHCI=y +CONFIG_USB_HID=y +CONFIG_USB_HUB=y +CONFIG_USB_MSC=y +CONFIG_LITTLE_ENDIAN=y +CONFIG_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 38bda55..02c9449 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -217,6 +217,18 @@ struct cb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define CB_TAG_X86_ROM_MTRR 0x0021 +struct cb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. If one wants to + * enable caching the ROM, the variable MTRR needs to be set to + * write-protect. To disable the caching after enabling set the + * type to uncacheable. */ + uint32_t index; +}; + + #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e05ef9f..fd60dc3 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -99,6 +99,11 @@ struct sysinfo_t { void *vdat_addr; u32 vdat_size; #endif + +#ifdef CONFIG_ARCH_X86 + int x86_rom_var_mtrr_index; +#endif + void *tstamp_table; void *cbmem_cons; void *mrc_cache;

1 0

Patch set updated for coreboot: e3a9452 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2890 -gerrit commit e3a94529306b2d8ee7c7cd67c88143ad364fac25 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 22:09:46 2013 -0500 resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR] The IORESOURCE_UMA_FB and IORESOURCE_IGNORE_MTRR attributes on a resource provided hints to the MTRR algorithm. The IORESOURCE_UMA_FB directed the MTRR algorithm to setup a uncacheable space for the resource. The IORESOURCE_IGNORE_MTRR directed the MTRR algorithm to ignore this resource as it was used reserving RAM space. Now that the optimizing MTRR algorithm is in place there isn't a need for these flags. All IORESOURCE_IGNORE_MTRR users are handled by the MTRR code merging resources of the same cacheable type. The users of the IORESOURCE_UMA_FB will find that the default MTRR type calculation means there isn't a need for this flag any more. Change-Id: I4f62192edd9a700cb80fa7569caf49538f9b83b7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/device/device.h | 6 +++--- src/include/device/resource.h | 2 -- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index b8dfbf5..44a9742 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -207,16 +207,16 @@ void fixed_mem_resource(device_t dev, unsigned long index, fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) #define reserved_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE) #define bad_ram_resource(dev, idx, basek, sizek) \ reserved_ram_resource((dev), (idx), (basek), (sizek)) #define uma_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) #define mmio_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index ea1bab5..6b66605 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,8 +21,6 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ -#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */

1 0

Patch set updated for coreboot: cae429f x86: add rom cache variable MTRR index to tables
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2919 -gerrit commit cae429f0df2e2e721c82a20fd16db615cc76d63b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 13:09:39 2013 -0500 x86: add rom cache variable MTRR index to tables Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 5 +++++ src/include/boot/coreboot_tables.h | 8 ++++++++ src/include/cpu/x86/mtrr.h | 3 +++ src/lib/coreboot_table.c | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index c847d2c..d8c5da1 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void) #if CONFIG_CACHE_ROM static long rom_cache_mtrr = -1; +long x86_mtrr_rom_cache_var_index(void) +{ + return rom_cache_mtrr; +} + void x86_mtrr_enable_rom_caching(void) { msr_t msr_val; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f624ac1..a7e4ab0 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -250,6 +250,14 @@ struct lb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define LB_TAG_X86_ROM_MTRR 0x0021 +struct lb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. */ + uint32_t index; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bff736d..15a5cad 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -78,9 +78,12 @@ int x86_mtrr_check(void); #if CONFIG_CACHE_ROM void x86_mtrr_enable_rom_caching(void); void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); #else static inline void x86_mtrr_enable_rom_caching(void) {} static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } #endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index b9a82a8..765c510 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -40,6 +40,9 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#if CONFIG_ARCH_X86 +#include <cpu/x86/mtrr.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -237,6 +240,24 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ +static void lb_x86_rom_cache(struct lb_header *header) +{ +#if CONFIG_ARCH_X86 + long mtrr_index; + struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; + + mtrr_index = x86_mtrr_rom_cache_var_index(); + + if (mtrr_index < 0) + return; + + lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); + lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; + lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); + lb_x86_rom_mtrr->index = mtrr_index; +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -539,6 +560,8 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); + /* Communicate x86 variable MTRR ROM cache information. */ + lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */

1 0

Patch set updated for coreboot: 143fc0c x86: mtrr: add CONFIG_CACHE_ROM support
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2918 -gerrit commit 143fc0c2d44827ba2180bda74d53e9edc9b93886 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 26 12:47:47 2013 -0500 x86: mtrr: add CONFIG_CACHE_ROM support The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR specifically for setting up write-protect cachine of the ROM. It is assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole area should be cached just under 4GiB. If enabled, the MTRR code will allocate but not enable rom caching. It is up to the callers of the MTRR code to explicitly enable (and disable afterwards) through the use of 2 new functions: - x86_mtrr_enable_rom_caching() - x86_mtrr_disable_rom_caching() Additionally, the CACHE_ROM option is exposed to the config menu so that it is not just selected by the chipset or board. The reasoning is that through a multitude of options CACHE_ROM may not be appropriate for enabling. Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 5 +++- src/cpu/x86/mtrr/mtrr.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 16 +++++++++++++ 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 8f05bf3..4c5176b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -56,8 +56,11 @@ config LOGICAL_CPUS default y config CACHE_ROM - bool + bool "Allow for caching system ROM." default n + help + When selected a variable range MTRR is allocated for coreboot and + the bootloader enables caching of the system ROM for faster access. config SMM_TSEG bool diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8bf69c5..c847d2c 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -163,6 +163,16 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); +#if CONFIG_CACHE_ROM + /* Add a write-protect region covering the ROM size + * when CONFIG_CACHE_ROM is enabled. The ROM is assumed + * to be located at 4GiB - rom size. */ + resource_t rom_base = RANGE_TO_PHYS_ADDR( + RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); + memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); +#endif + /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -335,6 +345,44 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } +/* Keep track of the MTRR that covers the ROM for caching purposes. */ +#if CONFIG_CACHE_ROM +static long rom_cache_mtrr = -1; + +void x86_mtrr_enable_rom_caching(void) +{ + msr_t msr_val; + unsigned long index; + + if (rom_cache_mtrr < 0) + return; + + index = rom_cache_mtrr; + disable_cache(); + msr_val = rdmsr(MTRRphysBase_MSR(index)); + msr_val.lo &= ~0xff; + msr_val.lo |= MTRR_TYPE_WRPROT; + wrmsr(MTRRphysBase_MSR(index), msr_val); + enable_cache(); +} + +void x86_mtrr_disable_rom_caching(void) +{ + msr_t msr_val; + unsigned long index; + + if (rom_cache_mtrr < 0) + return; + + index = rom_cache_mtrr; + disable_cache(); + msr_val = rdmsr(MTRRphysBase_MSR(index)); + msr_val.lo &= ~0xff; + wrmsr(MTRRphysBase_MSR(index), msr_val); + enable_cache(); +} +#endif + struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -382,6 +430,17 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; +#if CONFIG_CACHE_ROM + /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing + * one to turn on caching for faster ROM access. However, it is + * left to the MTRR callers to enable it. */ + if (mtrr_type == MTRR_TYPE_WRPROT) { + mtrr_type = MTRR_TYPE_UNCACHEABLE; + if (rom_cache_mtrr < 0) + rom_cache_mtrr = var_state->mtrr_index; + } +#endif + printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 618a93c..bff736d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,6 +52,10 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. + * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling + * the caching of the ROM. However, it is set to uncacheable (UC). It + * is the responsiblity of the caller to enable it by calling + * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -67,6 +71,18 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); +/* ROM caching can be used after variable MTRRs are set up. Beware that + * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on + * one's IO hole size and WRCOMB resources. Be sure to check the console + * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. */ +#if CONFIG_CACHE_ROM +void x86_mtrr_enable_rom_caching(void); +void x86_mtrr_disable_rom_caching(void); +#else +static inline void x86_mtrr_enable_rom_caching(void) {} +static inline void x86_mtrr_disable_rom_caching(void) {} +#endif /* CONFIG_CACHE_ROM */ + #endif #if !defined(CONFIG_RAMTOP)

1 0

Patch set updated for coreboot: 323201d coreboot table: use memrange library
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2917 -gerrit commit 323201d5213f27ae44b5477c77049080d3f97c17 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 23 00:06:36 2013 -0500 coreboot table: use memrange library Use the memrange library for keeping track of the address space region types. The memrange library is built to do just that for both the MTRR code and the coreboot memtable code. Change-Id: Iee2a7c37a3f4cf388db87ce40b580f274384ff3c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/coreboot_table.c | 271 +++++++++-------------------------------------- 1 file changed, 53 insertions(+), 218 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 84eb5a6..b9a82a8 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -29,6 +29,7 @@ #include <stdlib.h> #include <cbfs.h> #include <cbmem.h> +#include <memrange.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif @@ -356,54 +357,7 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header return forward; } -static void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - int entries; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - mem->map[entries].start = pack_lb64(start); - mem->map[entries].size = pack_lb64(size); - mem->map[entries].type = type; - mem->size += sizeof(mem->map[0]); -} - -static void lb_reserve_table_memory(struct lb_header *head) -{ -/* Dynamic cbmem has already reserved the memory where the coreboot tables - * reside. Therefore, there is nothing to fix up. */ -#if !CONFIG_DYNAMIC_CBMEM - struct lb_record *last_rec; - struct lb_memory *mem; - uint64_t start; - uint64_t end; - int i, entries; - - last_rec = lb_last_record(head); - mem = get_lb_mem(); - start = (unsigned long)head; - end = (unsigned long)last_rec; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - /* Resize the right two memory areas so this table is in - * a reserved area of memory. Everything has been carefully - * setup so that is all we need to do. - */ - for(i = 0; i < entries; i++ ) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - /* Does this area need to be expanded? */ - if (map_end == start) { - mem->map[i].size = pack_lb64(end - map_start); - } - /* Does this area need to be contracted? */ - else if (map_start == start) { - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - } -#endif -} - -static unsigned long lb_table_fini(struct lb_header *head, int fixup) +static unsigned long lb_table_fini(struct lb_header *head) { struct lb_record *rec, *first_rec; rec = lb_last_record(head); @@ -411,9 +365,6 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup) head->table_bytes += rec->size; } - if (fixup) - lb_reserve_table_memory(head); - first_rec = lb_first_record(head); head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; @@ -424,128 +375,53 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup) return (unsigned long)rec + rec->size; } -static void lb_cleanup_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i, j; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Sort the lb memory ranges */ - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - for(j = i + 1; j < entries; j++) { - uint64_t temp_start = unpack_lb64(mem->map[j].start); - if (temp_start < entry_start) { - struct lb_memory_range tmp; - tmp = mem->map[i]; - mem->map[i] = mem->map[j]; - mem->map[j] = tmp; - } - } - } +/* Routines to extract part so the coreboot table or + * information from the coreboot table after we have written it. + * Currently get_lb_mem relies on a global we can change the + * implementaiton. + */ +static struct lb_memory *mem_ranges = NULL; - /* Merge adjacent entries */ - for(i = 0; (i + 1) < entries; i++) { - uint64_t start, end, nstart, nend; - if (mem->map[i].type != mem->map[i + 1].type) { - continue; - } - start = unpack_lb64(mem->map[i].start); - end = start + unpack_lb64(mem->map[i].size); - nstart = unpack_lb64(mem->map[i + 1].start); - nend = nstart + unpack_lb64(mem->map[i + 1].size); - if ((start <= nstart) && (end >= nstart)) { - if (start > nstart) { - start = nstart; - } - if (end < nend) { - end = nend; - } - /* Record the new region size */ - mem->map[i].start = pack_lb64(start); - mem->map[i].size = pack_lb64(end - start); - - /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], - ((entries - i - 2) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* See if I can merge with the next entry as well */ - i -= 1; - } - } +struct lb_memory *get_lb_mem(void) +{ + return mem_ranges; } -static void lb_remove_memory_range(struct lb_memory *mem, - uint64_t start, uint64_t size) +/* This structure keeps track of the coreboot table memory ranges. */ +static struct memranges lb_ranges; + +static struct lb_memory *build_lb_mem(struct lb_header *head) { - uint64_t end; - int entries; - int i; + struct lb_memory *mem; - end = start + size; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Remove a reserved area from the memory map */ - for(i = 0; i < entries; i++) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - if ((start <= map_start) && (end >= map_end)) { - /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], - ((entries - i - 1) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* Since the index will disappear revisit what will appear here */ - i -= 1; - } - else if ((start > map_start) && (end < map_end)) { - /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], - ((entries - i) * sizeof(mem->map[0]))); - mem->size += sizeof(mem->map[0]); - entries += 1; - /* Update the first map entry */ - mem->map[i].size = pack_lb64(start - map_start); - /* Update the second map entry */ - mem->map[i + 1].start = pack_lb64(end); - mem->map[i + 1].size = pack_lb64(map_end - end); - /* Don't bother with this map entry again */ - i += 1; - } - else if ((start <= map_start) && (end > map_start)) { - /* Shrink the start of the memory range */ - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - else if ((start < map_end) && (start > map_start)) { - /* Shrink the end of the memory range */ - mem->map[i].size = pack_lb64(start - map_start); - } - } -} + /* Record where the lb memory ranges will live */ + mem = lb_memory(head); + mem_ranges = mem; -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - lb_remove_memory_range(mem, start, size); - lb_memory_range(mem, type, start, size); - lb_cleanup_memory_ranges(mem); + /* Fill the memory map out. The order of operations is important in + * that each overlapping range will take over the next. Therefore, + * add cacheable resources as RAM then add the reserved resources. */ + memranges_init(&lb_ranges, IORESOURCE_CACHEABLE, + IORESOURCE_CACHEABLE, LB_MEM_RAM); + memranges_add_resources(&lb_ranges, IORESOURCE_RESERVE, + IORESOURCE_RESERVE, LB_MEM_RESERVED); + + return mem; } -static void lb_dump_memory_ranges(struct lb_memory *mem) +static void commit_lb_memory(struct lb_memory *mem) { - int entries; + struct range_entry *r; + struct lb_memory_range *lb_r; int i; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - printk(BIOS_DEBUG, "coreboot memory table:\n"); - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - uint64_t entry_size = unpack_lb64(mem->map[i].size); + lb_r = &mem->map[0]; + i = 0; + + memranges_each_entry(r, &lb_ranges) { const char *entry_type; - switch (mem->map[i].type) { + switch (range_entry_tag(r)) { case LB_MEM_RAM: entry_type="RAM"; break; case LB_MEM_RESERVED: entry_type="RESERVED"; break; case LB_MEM_ACPI: entry_type="ACPI"; break; @@ -557,58 +433,25 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) } printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, entry_start, entry_start+entry_size-1, entry_type); + i, range_entry_base(r), range_entry_end(r)-1, + entry_type); - } -} - -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementaiton. - */ -static struct lb_memory *mem_ranges = NULL; - -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} + lb_r->start = pack_lb64(range_entry_base(r)); + lb_r->size = pack_lb64(range_entry_size(r)); + lb_r->type = range_entry_tag(r); -static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); -} - -static struct lb_memory *build_lb_mem(struct lb_header *head) -{ - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; - - /* Build the raw table of memory */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); - return mem; + i++; + lb_r++; + mem->size += sizeof(struct lb_memory_range); + } } -static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size) { - struct lb_memory *mem = gp; - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); + memranges_insert(&lb_ranges, start, size, type); } -static void add_lb_reserved(struct lb_memory *mem) -{ - /* Add reserved ranges */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, - lb_add_rsvd_range, mem); -} unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, @@ -623,7 +466,7 @@ unsigned long write_coreboot_table( head = lb_table_init(low_table_end); lb_forward(head, (struct lb_header*)rom_table_end); - low_table_end = (unsigned long) lb_table_fini(head, 0); + low_table_end = (unsigned long) lb_table_fini(head); printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", low_table_end); low_table_end = ALIGN(low_table_end, 4096); @@ -682,17 +525,9 @@ unsigned long write_coreboot_table( high_tables_base, high_tables_size); #endif /* CONFIG_DYNAMIC_CBMEM */ - /* Add reserved regions */ - add_lb_reserved(mem); - - lb_dump_memory_ranges(mem); - - /* Note: - * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. - * I can trivially fixup the reserved memory ranges to hold the correct - * size of the coreboot table. - */ + /* No other memory areas can be added after the memory table has been + * committed as the entries won't show up in the serialize mem table. */ + commit_lb_memory(mem); /* Record our motherboard */ lb_mainboard(head); @@ -721,5 +556,5 @@ unsigned long write_coreboot_table( add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); + return lb_table_fini(head); }

1 0

Patch set updated for coreboot: 10965d3 coreboot: add headers from Linux kernel
by Aaron Durbin 27 Mar '13

27 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2887 -gerrit commit 10965d3e9605754b52ebe909c44e567cda2c35f9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 22 20:37:04 2013 -0500 coreboot: add headers from Linux kernel The linux kernel has some helpful data structures and functions defined. util.h is a copy of kernel.h with the kernel-specific bits removed. list.h is the kernel's linked list implementation. These headers are going to be used in subsequent patches. Change-Id: Ic8b991ba855ea53a1e6936edab3c0a962724fa43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/list.h | 740 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/include/util.h | 252 ++++++++++++++++++ 2 files changed, 992 insertions(+) diff --git a/src/include/list.h b/src/include/list.h new file mode 100644 index 0000000..67c10e3 --- /dev/null +++ b/src/include/list.h @@ -0,0 +1,740 @@ +#ifndef _LINUX_LIST_H +#define _LINUX_LIST_H + +/* Linux kernel linked list support. */ +#include <stddef.h> +#include <util.h> + +struct list_head { + struct list_head *next, *prev; +}; + +struct hlist_head { + struct hlist_node *first; +}; + +struct hlist_node { + struct hlist_node *next, **pprev; +}; + +# define POISON_POINTER_DELTA 0 + +/* + * These are non-NULL pointers that will result in page faults + * under normal circumstances, used to verify that nobody uses + * non-initialized list entries. + */ +#define LIST_POISON1 ((void *) 0x00100100 + POISON_POINTER_DELTA) +#define LIST_POISON2 ((void *) 0x00200200 + POISON_POINTER_DELTA) + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} +#else +extern void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next); +#endif + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_del_entry(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); +} + +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = LIST_POISON1; + entry->prev = LIST_POISON2; +} +#else +extern void __list_del_entry(struct list_head *entry); +extern void list_del(struct list_head *entry); +#endif + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, + struct list_head *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *new) +{ + list_replace(old, new); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del_entry(entry); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del_entry(list); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del_entry(list); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +static inline void list_rotate_left(struct list_head *head) +{ + struct list_head *first; + + if (!list_empty(head)) { + first = head->next; + list_move_tail(first, head); + } +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant doesn't differ from list_for_each() any more. + * We don't do prefetching in either case. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue - continue list iteration safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from - iterate over list from current point safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +/** + * list_safe_reset_next - reset a stale list_for_each_entry_safe loop + * @pos: the loop cursor used in the list_for_each_entry_safe loop + * @n: temporary storage used in list_for_each_entry_safe + * @member: the name of the list_struct within the struct. + * + * list_safe_reset_next is not safe to use in general if the list may be + * modified concurrently (eg. the lock is dropped in the loop body). An + * exception to this is if the cursor element (pos) is pinned in the list, + * and list_safe_reset_next is called after re-taking the lock and before + * completing the current iteration of the loop body. + */ +#define list_safe_reset_next(pos, n, member) \ + n = list_entry(pos->member.next, typeof(*pos), member) + +/* + * Double linked lists with a single pointer list head. + * Mostly useful for hash tables where the two pointer list head is + * too wasteful. + * You lose the ability to access the tail in O(1). + */ + +#define HLIST_HEAD_INIT { .first = NULL } +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) +static inline void INIT_HLIST_NODE(struct hlist_node *h) +{ + h->next = NULL; + h->pprev = NULL; +} + +static inline int hlist_unhashed(const struct hlist_node *h) +{ + return !h->pprev; +} + +static inline int hlist_empty(const struct hlist_head *h) +{ + return !h->first; +} + +static inline void __hlist_del(struct hlist_node *n) +{ + struct hlist_node *next = n->next; + struct hlist_node **pprev = n->pprev; + *pprev = next; + if (next) + next->pprev = pprev; +} + +static inline void hlist_del(struct hlist_node *n) +{ + __hlist_del(n); + n->next = LIST_POISON1; + n->pprev = LIST_POISON2; +} + +static inline void hlist_del_init(struct hlist_node *n) +{ + if (!hlist_unhashed(n)) { + __hlist_del(n); + INIT_HLIST_NODE(n); + } +} + +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) +{ + struct hlist_node *first = h->first; + n->next = first; + if (first) + first->pprev = &n->next; + h->first = n; + n->pprev = &h->first; +} + +/* next must be != NULL */ +static inline void hlist_add_before(struct hlist_node *n, + struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + next->pprev = &n->next; + *(n->pprev) = n; +} + +static inline void hlist_add_after(struct hlist_node *n, + struct hlist_node *next) +{ + next->next = n->next; + n->next = next; + next->pprev = &n->next; + + if(next->next) + next->next->pprev = &next->next; +} + +/* after that we'll appear to be on some hlist and hlist_del will work */ +static inline void hlist_add_fake(struct hlist_node *n) +{ + n->pprev = &n->next; +} + +/* + * Move a list from one list head to another. Fixup the pprev + * reference of the first entry if it exists. + */ +static inline void hlist_move_list(struct hlist_head *old, + struct hlist_head *new) +{ + new->first = old->first; + if (new->first) + new->first->pprev = &new->first; + old->first = NULL; +} + +#define hlist_entry(ptr, type, member) container_of(ptr,type,member) + +#define hlist_for_each(pos, head) \ + for (pos = (head)->first; pos ; pos = pos->next) + +#define hlist_for_each_safe(pos, n, head) \ + for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ + pos = n) + +/** + * hlist_for_each_entry - iterate over list of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry(tpos, pos, head, member) \ + for (pos = (head)->first; \ + pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_continue - iterate over a hlist continuing after current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_continue(tpos, pos, member) \ + for (pos = (pos)->next; \ + pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_from - iterate over a hlist continuing from current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_from(tpos, pos, member) \ + for (; pos && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @n: another &struct hlist_node to use as temporary storage + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ + for (pos = (head)->first; \ + pos && ({ n = pos->next; 1; }) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = n) + +#endif diff --git a/src/include/util.h b/src/include/util.h new file mode 100644 index 0000000..eda053b --- /dev/null +++ b/src/include/util.h @@ -0,0 +1,252 @@ +#ifndef _LINUX_KERNEL_H +#define _LINUX_KERNEL_H + +#include <stdint.h> + +#define BITS_PER_LONG 32 +/* This code is taken from the linux kernel, kernel.h, with some function + * definitions and other non-applicable items culled out. */ + +#define USHRT_MAX ((u16)(~0U)) +#define SHRT_MAX ((s16)(USHRT_MAX>>1)) +#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) +#define INT_MAX ((int)(~0U>>1)) +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (~0U) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) +#define LLONG_MAX ((long long)(~0ULL>>1)) +#define LLONG_MIN (-LLONG_MAX - 1) +#define ULLONG_MAX (~0ULL) +#define SIZE_MAX (~(size_t)0) + +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +/* + * This looks more complex than it should be. But we need to + * get the type for the ~ right in round_down (it needs to be + * as wide as the result!), and we want to evaluate the macro + * arguments just once each. + */ +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define DIV_ROUND_UP_ULL(ll,d) \ + ({ unsigned long long _tmp = (ll)+(d)-1; do_div(_tmp, d); _tmp; }) + +#if BITS_PER_LONG == 32 +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d) +#else +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d) +#endif + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) +#define rounddown(x, y) ( \ +{ \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ +} \ +) +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(divisor) __divisor = divisor; \ + (((x) + ((__divisor) / 2)) / (__divisor)); \ +} \ +) + +/* + * Multiplies an integer by a fraction, while avoiding unnecessary + * overflow or loss of precision. + */ +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((u32)(n)) + +/* + * abs() handles unsigned and signed longs, ints, shorts and chars. For all + * input types abs() returns a signed long. + * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64() + * for those. + */ +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define abs64(x) ({ \ + s64 __x = (x); \ + (__x < 0) ? -__x : __x; \ + }) + +/* + * min()/max()/clamp() macros that also do + * strict type-checking.. See the + * "unnecessary" pointer comparison. + */ +#define min(x, y) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void) (&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; }) + +#define max(x, y) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void) (&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; }) + +#define min3(x, y, z) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + typeof(z) _min3 = (z); \ + (void) (&_min1 == &_min2); \ + (void) (&_min1 == &_min3); \ + _min1 < _min2 ? (_min1 < _min3 ? _min1 : _min3) : \ + (_min2 < _min3 ? _min2 : _min3); }) + +#define max3(x, y, z) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + typeof(z) _max3 = (z); \ + (void) (&_max1 == &_max2); \ + (void) (&_max1 == &_max3); \ + _max1 > _max2 ? (_max1 > _max3 ? _max1 : _max3) : \ + (_max2 > _max3 ? _max2 : _max3); }) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does strict typechecking of min/max to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, min, max) ({ \ + typeof(val) __val = (val); \ + typeof(min) __min = (min); \ + typeof(max) __max = (max); \ + (void) (&__val == &__min); \ + (void) (&__val == &__max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) + +#define max_t(type, x, y) ({ \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1: __max2; }) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, min, max) ({ \ + type __val = (val); \ + type __min = (min); \ + type __max = (max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @min: minimum allowable value + * @max: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, min, max) ({ \ + typeof(val) __val = (val); \ + typeof(val) __min = (min); \ + typeof(val) __max = (max); \ + __val = __val < __min ? __min: __val; \ + __val > __max ? __max: __val; }) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif

1 0

← Newer
1
...
16
17
18
19
20
21
22
...
45
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2013