the following patch was just integrated into master:
commit 12785d9601d8fdfe6f12289b4fd7001f304862f5
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Fri Nov 8 10:13:50 2013 -0800
util/xcompile/xcompile: set up for aarch64
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64
This now finds the right files for building on aarch64
This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.
Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: http://review.coreboot.org/4035
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
See http://review.coreboot.org/4035 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4035
-gerrit
commit 2ff1d81ede248a4bf8cc5682c2a984923e4e8d13
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Fri Nov 8 10:13:50 2013 -0800
util/xcompile/xcompile: set up for aarch64
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64
This now finds the right files for building on aarch64
This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.
Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
---
util/xcompile/xcompile | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 5388889..df7d558 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -110,6 +110,10 @@ detect_special_flags() {
ARMFLAGS=""
testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
;;
+ aarch64 )
+ ARMFLAGS=""
+ testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
+ ;;
esac
}
@@ -136,7 +140,7 @@ touch "$TMPFILE"
trap clean_up EXIT
# Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7"
+SUPPORTED_ARCHITECTURE="x86 armv7 aarch64"
# ARM Architecture
TARCH_armv7="armv7"
@@ -144,6 +148,12 @@ TBFDARCH_armv7="littlearm"
TCLIST_armv7="armv7a armv7-a"
TWIDTH_armv7="32"
+# AARCH64 -- armv8
+TARCH_aarch64="aarch64"
+TBFDARCH_aarch64="littleaarch64"
+TCLIST_aarch64="aarch64"
+TWIDTH_aarch64="64"
+
# X86 Architecture
TARCH_x86="i386"
TBFDARCH_x86="i386"
@@ -170,6 +180,7 @@ for architecture in $SUPPORTED_ARCHITECTURE; do
for toolchain in $TCLIST; do
search="$search $XGCCPATH$toolchain-elf-"
search="$search $toolchain-elf-"
+ search="$search $toolchain-linux-gnu-"
search="$search $XGCCPATH$toolchain-eabi-"
search="$search $toolchain-eabi-"
done
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4035
-gerrit
commit ff153c42f5e4e4ff82586b7cb532ff46c186a99c
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Fri Nov 8 10:13:50 2013 -0800
util/xcompile/xcompile: set up for aarch64
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64
This now finds the right files for building on aarch64
This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.
Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
---
util/xcompile/xcompile | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 5388889..a60f3cb 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -110,6 +110,10 @@ detect_special_flags() {
ARMFLAGS=""
testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
;;
+ aarch64 )
+ ARMFLAGS=""
+ testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
+ ;;
esac
}
@@ -136,7 +140,7 @@ touch "$TMPFILE"
trap clean_up EXIT
# Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7"
+SUPPORTED_ARCHITECTURE="x86 armv7 aarch64"
# ARM Architecture
TARCH_armv7="armv7"
@@ -144,6 +148,12 @@ TBFDARCH_armv7="littlearm"
TCLIST_armv7="armv7a armv7-a"
TWIDTH_armv7="32"
+# AARCH64 -- armv8
+TARCH_aarch64="aarch64"
+TBFDARCH_aarch64="elf64-littleaarch64"
+TCLIST_aarch64="aarch64 aarch64-linux-gnu"
+TWIDTH_aarch64="64"
+
# X86 Architecture
TARCH_x86="i386"
TBFDARCH_x86="i386"
@@ -170,6 +180,7 @@ for architecture in $SUPPORTED_ARCHITECTURE; do
for toolchain in $TCLIST; do
search="$search $XGCCPATH$toolchain-elf-"
search="$search $toolchain-elf-"
+ search="$search $toolchain-"
search="$search $XGCCPATH$toolchain-eabi-"
search="$search $toolchain-eabi-"
done
the following patch was just integrated into master:
commit 2a58ecde78350902ac47145a3f2dba063bce3375
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Tue Oct 29 17:32:00 2013 -0600
Add new finalize functions for devices and chips
Many chipset devices require additional configuration after
device init. It is not uncommmon for a device early in the devicetree
list to need to change a setting after a device later in the tree does
PCI init. A final function call has been added to device ops to handle
this case. It is called prior to coreboot table setup.
Another problem that is often seen is that the chipset or mainboard
need to do some final cleanup just before loading the OS. The chip
finalize has been added for this case. It is call after all coreboot
tables are setup and the payload is ready to be called.
Similar functionality could be implemented with the hardwaremain
states, but those don't fit well in the device tree function pointer
structure and should be used sparingly.
Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/4012
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4012 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4035
-gerrit
commit 15e162025bf05b49d74d7e1b59c4d8ede9241a39
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Fri Nov 8 10:13:50 2013 -0800
util/xcompile/xcompile: try, and fail, to set it up for aarch64
Not to be comitted until fixed.
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64
I've added what I think ought to work but it fails to find it.
One thing I've noticed is that gcc for the test .c file
is only run AFTER the first instance of testas is run, which
I don't understand. But the assembly source in /tmp that testas
runs against, for aarch64, is a 0-byte file.
This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.
Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
---
util/xcompile/xcompile | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 5388889..a60f3cb 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -110,6 +110,10 @@ detect_special_flags() {
ARMFLAGS=""
testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
;;
+ aarch64 )
+ ARMFLAGS=""
+ testcc "$CC" "$CFLAGS $ARMFLAGS"&&CFLAGS="$CFLAGS $ARMFLAGS"
+ ;;
esac
}
@@ -136,7 +140,7 @@ touch "$TMPFILE"
trap clean_up EXIT
# Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7"
+SUPPORTED_ARCHITECTURE="x86 armv7 aarch64"
# ARM Architecture
TARCH_armv7="armv7"
@@ -144,6 +148,12 @@ TBFDARCH_armv7="littlearm"
TCLIST_armv7="armv7a armv7-a"
TWIDTH_armv7="32"
+# AARCH64 -- armv8
+TARCH_aarch64="aarch64"
+TBFDARCH_aarch64="elf64-littleaarch64"
+TCLIST_aarch64="aarch64 aarch64-linux-gnu"
+TWIDTH_aarch64="64"
+
# X86 Architecture
TARCH_x86="i386"
TBFDARCH_x86="i386"
@@ -170,6 +180,7 @@ for architecture in $SUPPORTED_ARCHITECTURE; do
for toolchain in $TCLIST; do
search="$search $XGCCPATH$toolchain-elf-"
search="$search $toolchain-elf-"
+ search="$search $toolchain-"
search="$search $XGCCPATH$toolchain-eabi-"
search="$search $toolchain-eabi-"
done
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4027
-gerrit
commit 2045ccef11bfed59c20433236285e66672bacd26
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Tue Nov 5 17:47:37 2013 -0700
emeraldlake2: Clean up COM port enable
Remove the COM port enable loop. There is no need to
search for the port when it is needed and known by the
GPIO function.
Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
---
src/mainboard/intel/emeraldlake2/romstage.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 7691116..363299d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -42,31 +42,29 @@
#include <vendorcode/google/chromeos/chromeos.h>
#endif
+#define SIO_PORT 0x164e
+
static void pch_enable_lpc(void)
{
device_t dev = PCH_LPC_DEV;
- int i;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
- /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */
- u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN;
+ /* Enable SuperIO + PS/2 Keyboard/Mouse */
+ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
/* Map 256 bytes at 0x1600 to the LPC bus. */
pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
- /* Map a range for the runtime registers to the LPC bus. */
+ /* Map a range for the runtime_port registers to the LPC bus. */
pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
- for (i = 0; i < ARRAY_SIZE(sio1007_lpc_ports); i++) {
- if (sio1007_enable_uart_at(sio1007_lpc_ports[i])) {
- /* Keep COMA UART enable bit on. */
- pci_write_config16(dev, LPC_EN,
- lpc_config | COMA_LPC_EN);
- break;
- }
+ /* Enable COM1 */
+ if (sio1007_enable_uart_at(SIO_PORT)) {
+ pci_write_config16(dev, LPC_EN,
+ lpc_config | COMA_LPC_EN);
}
}
@@ -132,7 +130,7 @@ static void early_pch_init(void)
static void setup_sio_gpios(void)
{
- const u16 port = 0x164e;
+ const u16 port = SIO_PORT;
const u16 runtime_port = 0x180;
/* Turn on configuration mode. */
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4014
-gerrit
commit 4de93aa141308e9f5316c2be2d95f37dae0870b6
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Wed Oct 30 16:18:07 2013 -0600
sio1007: Properly build '.c' files
Properly build the super i/o .c files. This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.
Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
---
src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
src/superio/smsc/sio1007/Makefile.inc | 21 +++++++++++++++++++++
src/superio/smsc/sio1007/chip.h | 26 ++++++++++++++++++++++++++
src/superio/smsc/sio1007/early_serial.c | 12 +++++-------
4 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 363299d..f116668 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -29,7 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include "superio/smsc/sio1007/early_serial.c"
+#include "superio/smsc/sio1007/chip.h"
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
diff --git a/src/superio/smsc/sio1007/Makefile.inc b/src/superio/smsc/sio1007/Makefile.inc
new file mode 100644
index 0000000..1068468
--- /dev/null
+++ b/src/superio/smsc/sio1007/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Sage Electronic Engineering LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c
+
diff --git a/src/superio/smsc/sio1007/chip.h b/src/superio/smsc/sio1007/chip.h
new file mode 100644
index 0000000..eee2811
--- /dev/null
+++ b/src/superio/smsc/sio1007/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_1007_CHIP_H
+#define SUPERIO_SMSC_1007_CHIP_H
+
+void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask);
+int sio1007_enable_uart_at(u16 port);
+
+#endif
diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c
index 859e351..d1d28b2 100644
--- a/src/superio/smsc/sio1007/early_serial.c
+++ b/src/superio/smsc/sio1007/early_serial.c
@@ -17,13 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*
- * The chip could be bootstrap mapped to one of four LPC addresses:
- * 0x2e, 0x4e, 0x162e, and 0x164e.
- */
-const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
+#include <stdint.h>
+#include <arch/io.h>
+#include "chip.h"
-static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
+void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
{
u8 reg_value;
@@ -34,7 +32,7 @@ static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
outb(reg_value, lpc_port + 1);
}
-static int sio1007_enable_uart_at(u16 port)
+int sio1007_enable_uart_at(u16 port)
{
/* Enable config mode. */
outb(0x55, port);