the following patch was just integrated into master:
commit d80cd2ad80b2b9debfce1fce5f94c773cb51c8cc
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 22 16:13:49 2013 -0700
slippy: Clean up for easier porting
Minor tweaks to variable names in the slippy mainboard
that make it easier to base a new board from without
as much renaming.
Also properly set up the thermal variables for the
thermal zone that is defined in ACPI instead of using
the generic setup from WTM2.
Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56328
Reviewed-on: http://review.coreboot.org/4183
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4183 for details.
-gerrit
the following patch was just integrated into master:
commit cfe0235c6fb5574b54139c6e7bd31da974e4ef23
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 21 10:11:07 2013 -0700
slippy: Run EC init as part of mainboard init step
This will log and clear EC events so they do not take effect
when the SMI handler is enabled.
Change-Id: I5ef563f7cedc8977410cc3f69e2655fc4e14c9eb
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56055
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4178
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4178 for details.
-gerrit
the following patch was just integrated into master:
commit 90bfbfa9bae901d006b5933d26fad3c7185170fc
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 21 08:05:39 2013 -0700
slippy: Update interrupt routing
The SerialIO devices have specific requirements for PCI
interrupt mode to use PIRQ{E,F,G,H} that are not being met.
D21:F0 uses PIRQE, which must not be shared with other PCH
D21:F1-F6 share PIRQF, which must not be shared with other PCH
D23:F0 uses PIRQH, which must not be shared with other PCH
- Fix D20IR -> D20IP typo
- Remove D25/EHCI2 as it does not exist
- Reorder other interrupts to clear PIRQE/PIRQF/PIRQH
Check device interrupts in the kernel
0: IO-APIC-edge timer
1: IO-APIC-edge i8042
8: IO-APIC-edge rtc0
9: IO-APIC-fasteoi acpi
16: IO-APIC-fasteoi ath9k
18: IO-APIC-fasteoi i801_smbus
19: IO-APIC-fasteoi ehci_hcd:usb1
21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1
40: PCI-MSI-edge PCIe PME
41: PCI-MSI-edge i915
42: PCI-MSI-edge ahci
43: PCI-MSI-edge xhci_hcd
44: PCI-MSI-edge snd_hda_intel
Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56028
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4176 for details.
-gerrit
the following patch was just integrated into master:
commit a54adc1bc78a4caa814be8e5a69d48e1f181952a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed May 15 17:02:23 2013 -0700
slippy: set PWM values
The dev screen was not displaying properly. With the
PWM values programmed the screen displays correctly.
Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51472
Reviewed-on: http://review.coreboot.org/4172
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4172 for details.
-gerrit
the following patch was just integrated into master:
commit 270881af741eaeae29a084bad351c7182bfde275
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 15 15:05:38 2013 -0700
slippy: Put SerialIO devices in PCI mode
The device at function 0 also needs to be enabled
or the kernel will ignore all other functions.
00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03)
00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03)
00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03)
Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51370
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4171
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4171 for details.
-gerrit
the following patch was just integrated into master:
commit ffa0fa4660c8c9e605773ce9ad21d5bef209613d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 10 11:00:56 2013 -0700
slippy: Add EC to the device tree
This lets the keyboard init get called properly.
Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50853
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4167
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4167 for details.
-gerrit
the following patch was just integrated into master:
commit 4d019c9ee2d5d25cc8eac2b97586f761b79e49b2
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri May 3 15:59:59 2013 -0700
slippy: Update SPD
Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50082
Reviewed-on: http://review.coreboot.org/4157
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4157 for details.
-gerrit
the following patch was just integrated into master:
commit f31fcbc832c45294f11541cd96a973d43108b1fa
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu May 2 10:40:49 2013 -0700
slippy: Add SPD data for on-board memory
Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49911
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4154
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4154 for details.
-gerrit
the following patch was just integrated into master:
commit e820a6ce833aacb0cf9500809b03493a01dcf9c0
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed May 1 11:11:10 2013 -0700
slippy: Add iSSD power sequencing
Without an LM10506-A the power sequencing for this
part needs to be done manually using GPIOs.
Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49648
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/4150 for details.
-gerrit