coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 3e996a5 haswell: Update ULT microcode to rev 'a'
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit 3e996a55cd7b6a3ff9a1b5f16fd3c2247ff6bda8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 30 11:09:57 2013 -0700 haswell: Update ULT microcode to rev 'a' Change-Id: I714208da23bf7cbd1232874c05ad3100551f5f7c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49647 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4146 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4146 for details. -gerrit

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Patch merged into coreboot/master: e1e87e0 haswell: Configure PCH power sharing for ULT
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit e1e87e0ed6280f168abd92edcd692aec4ead8fe8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 26 10:35:19 2013 -0700 haswell: Configure PCH power sharing for ULT This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4143 for details. -gerrit

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Patch merged into coreboot/master: f24262d haswell: calibrate 24MHz clock against BCLK
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit f24262d01822bd8634e44b5aab19dafe7e04ae72 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 10 14:59:21 2013 -0500 haswell: calibrate 24MHz clock against BCLK On haswell ULT systems there is a 24MHz clock that continuously runs when deep package c-states are entered. The 100MHz BCLK is shut down in the lower c-states. When the package wakes back up a conversion formula needs to be applied. The 24MHz calibration is done using the internal PCODE unit. Change-Id: I6be7702fb1de1429273724536f5af9125b98da64 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48292 Tested-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4136 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4136 for details. -gerrit

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Patch merged into coreboot/master: 7c35131 haswell: configure c-states
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit 7c351316429f8b991df7ea233a5528f4efb3b8e0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 10 14:46:25 2013 -0500 haswell: configure c-states The c-states are configured according to the BWG, however the package c-states are disabled as they currently cause platform instability. The exposed ACPI c-state to processor c-state mapping are as follows for ULT boards: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C7S long latency) ACPI(C3) = MWAIT(C10) The non-ULT boards have an expoed c-state mapping: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Included in this patch is removing the updating of current limit registers as some of the MSRs are different and the proper values are currently unknown. Lastly, some of the MSRs were renamed to match the BWG. Booted 3.8 kernel and used powertop to note package, core, and acpi c-state residency. Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48291 Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/4133 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4133 for details. -gerrit

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New patch to review for coreboot: f824551 no-car/cbmemc: Fix compilation
by Vladimir Serbinenko 24 Nov '13

24 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4267 -gerrit commit f824551b758e54b8521333ce00d4f7ac20b1482e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 24 09:41:32 2013 +0100 no-car/cbmemc: Fix compilation the part !CAR && PRE_RAM is obviously meant as dummies. Unfortunately cbmemc_tx_byte has wrong number of arguments and hence causes compilation failure. Found out when compiling for vexpress-a9. Change-Id: Ic84d142bac5c455c2371fbc9439c898de04a974e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/include/console/cbmem_console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 9e2f14e..69332aa 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -26,7 +26,7 @@ void cbmemc_tx_byte(unsigned char data); #else #define cbmemc_init() #define cbmemc_reinit() -#define cbmemc_tx_byte() +#define cbmemc_tx_byte(x) #endif #endif

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Patch merged into coreboot/master: 15de7cb lynxpoint: Add a function to set an individual GPIO
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit 15de7cb4224b6add9a65d083e9a2e8484ae511b8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 13:44:37 2013 -0700 lynxpoint: Add a function to set an individual GPIO This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4137 for details. -gerrit

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Patch set updated for coreboot: b843129 lynxpoint: Add a function to set an individual GPIO
by Alexandru Gagniuc 24 Nov '13

24 Nov '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4137 -gerrit commit b843129c153cd99eb849c413ec653e13250394f1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 13:44:37 2013 -0700 lynxpoint: Add a function to set an individual GPIO This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/gpio.c | 19 +++++++++++++++++++ src/southbridge/intel/lynxpoint/lp_gpio.c | 14 ++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 4 ++++ 3 files changed, 37 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index b492068..147a1c0 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -109,3 +109,22 @@ unsigned get_gpios(const int *gpio_num_array) } return vector; } + +void set_gpio(int gpio_num, int value) +{ + static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_base + gpio_reg_offsets[index]); + config &= ~(1 << bit); + config |= value << bit; + outl(config, gpio_base + gpio_reg_offsets[index]); +} diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index d64555e..b90e5ba 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -107,3 +107,17 @@ unsigned get_gpios(const int *gpio_num_array) } return vector; } + +void set_gpio(int gpio_num, int value) +{ + u16 gpio_base = get_gpio_base(); + u32 conf0; + + if (gpio_num > MAX_GPIO_NUMBER) + return; + + conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num)); + conf0 &= ~GPO_LEVEL_MASK; + conf0 |= value << GPO_LEVEL_SHIFT; + outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num)); +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c049573..4bdb926 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -193,6 +193,10 @@ int get_gpio(int gpio_num); * the array of gpio pin numbers to scan, terminated by -1. */ unsigned get_gpios(const int *gpio_num_array); +/* + * set GPIO pin value + */ +void set_gpio(int gpio_num, int value); #endif #define MAINBOARD_POWER_OFF 0

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Patch merged into coreboot/master: 55ad972 lynxpoint: Rework LP GPIO handling
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit 55ad9724322739a862745a71806af8d9a870601b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 23 13:43:23 2013 -0700 lynxpoint: Rework LP GPIO handling This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this. Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare. Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4138 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4138 for details. -gerrit

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Patch merged into coreboot/master: 0edc224 smi: Update mainboard_smi_gpi() to have 32bit argument
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit 0edc22490a643c4b4c6181c42eed375485f9e0e4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 29 15:04:30 2013 -0700 smi: Update mainboard_smi_gpi() to have 32bit argument With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4145 for details. -gerrit

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Patch merged into coreboot/master: a7e9a9b slippy: Add panel power sequence timings
by gerrit＠coreboot.org 24 Nov '13

24 Nov '13

the following patch was just integrated into master: commit a7e9a9b75f806b290ea4fbe22a03e3489b1931f1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 28 07:54:15 2013 -0700 slippy: Add panel power sequence timings These are placeholder values until we can configure for the exact panel. Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56807 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4196 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4196 for details. -gerrit

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coreboot-gerrit November 2013