coreboot-gerrit October 2013

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New patch to review for coreboot: 16447c8 get_bus_conf.c: Run files with spaces instead of tabulators through `indent -linux`
by Paul Menzel 18 Oct '13

18 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3979 -gerrit commit 16447c8da5637f7165c1600e5cc780914e7f96d7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Oct 18 09:42:55 2013 +0200 get_bus_conf.c: Run files with spaces instead of tabulators through `indent -linux` For the board Win Enterprises MB6047 board, the board Tyan S2891 (Thunder K8SRE) is taken as template [1]. During review it turned out, `get_bus_conf.c` has spaces instead of tabs in some lines. To not spread these coding style errors further, correct all `get_bus_conf.c` with spaces at the beginning of at least one line. `indent` from Debian package indent 2.2.11-4 is used for that with the following command. $ git grep -l ' ' src/mainboard/*/*/get_bus_conf.c | xargs indent -linux Please note that more errors than just the spaces at the beginning of lines are fixed by that. [1] http://review.coreboot.org/3974 Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 255 +++++++------- src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +- src/mainboard/broadcom/blast/get_bus_conf.c | 93 ++--- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 89 ++--- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 88 ++--- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 257 +++++++------- src/mainboard/msi/ms9185/get_bus_conf.c | 139 ++++---- src/mainboard/msi/ms9282/get_bus_conf.c | 104 +++--- src/mainboard/sunw/ultra40/get_bus_conf.c | 382 +++++++++++---------- src/mainboard/supermicro/h8dme/get_bus_conf.c | 119 +++---- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 119 +++---- src/mainboard/tyan/s2881/get_bus_conf.c | 102 +++--- src/mainboard/tyan/s2885/get_bus_conf.c | 114 +++--- src/mainboard/tyan/s2891/get_bus_conf.c | 212 ++++++------ src/mainboard/tyan/s2892/get_bus_conf.c | 196 +++++------ src/mainboard/tyan/s2895/get_bus_conf.c | 216 ++++++------ 16 files changed, 1269 insertions(+), 1218 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index d4f44c0..f5cd846 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -15,11 +15,10 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -27,8 +26,8 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -39,39 +38,37 @@ static unsigned hcdnx[] = // 0x20202020, }; - - static unsigned get_bus_conf_done = 0; static unsigned get_hcid(unsigned i) { - unsigned id = 0; + unsigned id = 0; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + device_t dev; - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - switch (dev->device) { - case 0x7458: //8132 - id = 1; - break; - case 0x7454: //8151 - id = 2; + switch (dev->device) { + case 0x7458: //8132 + id = 1; + break; + case 0x7454: //8151 + id = 2; break; - case 0x7450: //8131 - id = 3; - break; - } + case 0x7450: //8131 + id = 3; + break; + } - // we may need more way to find out hcid: subsystem id? GPIO read ? + // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. acpi table + // we need use id for 1. bus num, 2. mptable, 3. acpi table - return id; + return id; } void get_bus_conf(void) @@ -79,11 +76,12 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + device_t dev; int i, j; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -92,7 +90,7 @@ void get_bus_conf(void) m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -105,91 +103,106 @@ void get_bus_conf(void) m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8111_0 = m->bus_8132_0; - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); - } - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) { - m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) { - m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); - } - - /* HT chain 1 */ - j=0; - for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - // check hcid type here - sysconf.hcid[i] = get_hcid(i); - - switch(sysconf.hcid[i]) { - - case 1: //8132 - case 3: //8131 - - m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - - m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0)); - if (dev) { - m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); - if (dev) { - m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); - } - - break; - - case 2: //8151 - - m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - m->sbdn5[j] = sysconf.hcdn[i] & 0xff; - /* 8151 */ - dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0)); - - if (dev) { - m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); - } - - break; - } - - j++; - } + /* 8111 */ + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8111_0, sysconf.sbdn); + } + /* 8132-1 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0)); + if (dev) { + m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3); + } + + /* 8132-2 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0)); + if (dev) { + m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3 + 1); + } + + /* HT chain 1 */ + j = 0; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; + + // check hcid type here + sysconf.hcid[i] = get_hcid(i); + + switch (sysconf.hcid[i]) { + + case 1: //8132 + case 3: //8131 + + m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + + m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; + + /* 8132-1 */ + dev = + dev_find_slot(m->bus_8132a[j][0], + PCI_DEVFN(m->sbdn3a[j], 0)); + if (dev) { + m->bus_8132a[j][1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j]); + } + + /* 8132-2 */ + dev = + dev_find_slot(m->bus_8132a[j][0], + PCI_DEVFN(m->sbdn3a[j] + 1, 0)); + if (dev) { + m->bus_8132a[j][2] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j] + 1); + } + + break; + + case 2: //8151 + + m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + m->sbdn5[j] = sysconf.hcdn[i] & 0xff; + /* 8151 */ + dev = + dev_find_slot(m->bus_8151[j][0], + PCI_DEVFN(m->sbdn5[j] + 1, 0)); + + if (dev) { + m->bus_8151[j][1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8151[j][0], m->sbdn5[j] + 1); + } + + break; + } + + j++; + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -197,12 +210,12 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - m->apicid_8111 = apicid_base+0; - m->apicid_8132_1 = apicid_base+1; - m->apicid_8132_2 = apicid_base+2; - for(i=0;i<j;i++) { - m->apicid_8132a[i][0] = apicid_base + 3 + i*2; - m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1; - } + m->apicid_8111 = apicid_base + 0; + m->apicid_8132_1 = apicid_base + 1; + m->apicid_8132_2 = apicid_base + 2; + for (i = 0; i < j; i++) { + m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; + m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; + } } diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index 18de8ec..fd7d304 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -85,7 +85,7 @@ void get_bus_conf(void) get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */ + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */ sbdn = sysconf.sbdn; for (i = 0; i < 8; i++) diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 36959a4..5de8952 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -10,7 +10,6 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default unsigned char bus_bcm5780[7]; @@ -19,11 +18,9 @@ unsigned char bus_bcm5785_1 = 8; unsigned char bus_bcm5785_1_1 = 9; unsigned apicid_bcm5785[3]; - -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -32,9 +29,9 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -43,9 +40,8 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdn2; - +unsigned sbdn2; static unsigned get_bus_conf_done = 0; @@ -54,51 +50,56 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_bcm5780[0] = bus_bcm5785_0; - /* bcm5785 */ - dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0)); - if(dev) { - bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:07.0, using defaults\n", bus_bcm5785_0); - } - - /* bcm5780 */ - for(i = 1; i < 7; i++) { - dev = dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1,0)); - if(dev) { - bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + /* bcm5785 */ + dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d, 0)); + if (dev) { + bus_bcm5785_1_1 = + pci_read_config8(dev, PCI_SECONDARY_BUS); } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_bcm5780[i]); - } + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:07.0, using defaults\n", + bus_bcm5785_0); } + /* bcm5780 */ + for (i = 1; i < 7; i++) { + dev = + dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1, 0)); + if (dev) { + bus_bcm5780[i] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_bcm5780[i]); + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -106,6 +107,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - for(i=0;i<3;i++) - apicid_bcm5785[i] = apicid_base+i; + for (i = 0; i < 3; i++) + apicid_bcm5785[i] = apicid_base + i; } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index d2de5ca..9315cbd 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -33,17 +33,14 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_sis966[8]; //1 - unsigned apicid_sis966; - +unsigned char bus_sis966[8]; //1 +unsigned apicid_sis966; -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -52,10 +49,10 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, +// 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -72,51 +69,55 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - for(i=0; i<8; i++) { + for (i = 0; i < 8; i++) { bus_sis966[i] = 0; } bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* SIS966 */ - dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_sis966[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_sis966[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_sis966[2]++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_sis966[1] = 2; - bus_sis966[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_sis966[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } + /* SIS966 */ + dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x06, 0)); + if (dev) { + bus_sis966[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_sis966[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_sis966[2]++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06); + + bus_sis966[1] = 2; + bus_sis966[2] = 3; + } + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(bus_sis966[0], + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + if (dev) { + bus_sis966[i] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -124,6 +125,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_sis966 = apicid_base+0; + apicid_sis966 = apicid_base + 0; } diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index 8082255..c798415 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -31,17 +31,14 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; - +unsigned char bus_mcp55[8]; //1 +unsigned apicid_mcp55; -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -50,10 +47,10 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, +// 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -70,51 +67,54 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - for(i=0; i<8; i++) { + for (i = 0; i < 8; i++) { bus_mcp55[i] = 0; } bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_mcp55[2]++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_mcp55[1] = 2; - bus_mcp55[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } + /* MCP55 */ + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0)); + if (dev) { + bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_mcp55[2]++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06); + + bus_mcp55[1] = 2; + bus_mcp55[2] = 3; + } + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(bus_mcp55[0], + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + if (dev) { + bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -122,6 +122,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_mcp55 = apicid_base+0; + apicid_mcp55 = apicid_base + 0; } diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 4f63ff5..8868f46 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -15,23 +15,22 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, // SB chain m - 0x0000000, // HTX - 0x0000100, // co processor on socket 1 +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, // SB chain m + 0x0000000, // HTX + 0x0000100, // co processor on socket 1 // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, 0x20202020, 0x20202020, - 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -39,39 +38,37 @@ static unsigned hcdnx[] = // 0x20202020, }; - - static unsigned get_bus_conf_done = 0; static unsigned get_hcid(unsigned i) { - unsigned id = 0; + unsigned id = 0; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + device_t dev; - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - switch (dev->device) { - case 0x7458: //8132 - id = 1; - break; - case 0x7454: //8151 - id = 2; + switch (dev->device) { + case 0x7458: //8132 + id = 1; break; - case 0x7450: //8131 - id = 3; - break; - } + case 0x7454: //8151 + id = 2; + break; + case 0x7450: //8131 + id = 3; + break; + } - // we may need more way to find out hcid: subsystem id? GPIO read ? + // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. acpi table + // we need use id for 1. bus num, 2. mptable, 3. acpi table - return id; + return id; } void get_bus_conf(void) @@ -79,11 +76,12 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + device_t dev; int i, j; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -92,7 +90,7 @@ void get_bus_conf(void) m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -105,90 +103,105 @@ void get_bus_conf(void) m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8111_0 = m->bus_8132_0; - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); - } - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) { - m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) { - m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); - } - - /* HT chain 1 */ - j=0; - for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - // check hcid type here - sysconf.hcid[i] = get_hcid(i); - - switch(sysconf.hcid[i]) { - - case 1: //8132 - case 3: //8131 - - m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - - m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0)); - if (dev) { - m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); - if (dev) { - m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); - } - - break; - - case 2: //8151 - - m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - m->sbdn5[j] = sysconf.hcdn[i] & 0xff; - /* 8151 */ - dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0)); - - if (dev) { - m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); - } - - break; - } - - j++; - } + /* 8111 */ + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8111_0, sysconf.sbdn); + } + + /* 8132-1 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0)); + if (dev) { + m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3); + } + /* 8132-2 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0)); + if (dev) { + m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3 + 1); + } + + /* HT chain 1 */ + j = 0; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; + + // check hcid type here + sysconf.hcid[i] = get_hcid(i); + + switch (sysconf.hcid[i]) { + + case 1: //8132 + case 3: //8131 + + m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + + m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; + + /* 8132-1 */ + dev = + dev_find_slot(m->bus_8132a[j][0], + PCI_DEVFN(m->sbdn3a[j], 0)); + if (dev) { + m->bus_8132a[j][1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j]); + } + + /* 8132-2 */ + dev = + dev_find_slot(m->bus_8132a[j][0], + PCI_DEVFN(m->sbdn3a[j] + 1, 0)); + if (dev) { + m->bus_8132a[j][2] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j] + 1); + } + + break; + + case 2: //8151 + + m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + m->sbdn5[j] = sysconf.hcdn[i] & 0xff; + /* 8151 */ + dev = + dev_find_slot(m->bus_8151[j][0], + PCI_DEVFN(m->sbdn5[j] + 1, 0)); + + if (dev) { + m->bus_8151[j][1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8151[j][0], m->sbdn5[j] + 1); + } + + break; + } + + j++; + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -196,12 +209,12 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - m->apicid_8111 = apicid_base+0; - m->apicid_8132_1 = apicid_base+1; - m->apicid_8132_2 = apicid_base+2; - for(i=0;i<j;i++) { - m->apicid_8132a[i][0] = apicid_base + 3 + i*2; - m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1; - } + m->apicid_8111 = apicid_base + 0; + m->apicid_8132_1 = apicid_base + 1; + m->apicid_8132_2 = apicid_base + 2; + for (i = 0; i < j; i++) { + m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; + m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; + } } diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 7ed8600..3a70d83 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -38,11 +38,10 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -50,10 +49,10 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, + +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -62,73 +61,77 @@ static unsigned hcdnx[] = // 0x20202020, }; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { - unsigned apicid_base; - - device_t dev; - int i; - struct mb_sysconf_t *m; - - if(get_bus_conf_done==1) return; //do it only once - - get_bus_conf_done = 1; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 - - m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; - m->bus_bcm5780[0] = m->bus_bcm5785_0; - - /* bcm5785 */ - dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); - if(dev) { - m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); - } - - /* bcm5780 */ - for(i = 1; i < 7; i++) { - dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); - if(dev) { - m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); - } - } - + unsigned apicid_base; + + device_t dev; + int i; + struct mb_sysconf_t *m; + + if (get_bus_conf_done == 1) + return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + + m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_bcm5780[0] = m->bus_bcm5785_0; + + /* bcm5785 */ + dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd, 0)); + if (dev) { + m->bus_bcm5785_1_1 = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_bcm5785_0, sysconf.sbdn); + } + + /* bcm5780 */ + for (i = 1; i < 7; i++) { + dev = + dev_find_slot(m->bus_bcm5780[0], + PCI_DEVFN(m->sbdn2 + i - 1, 0)); + if (dev) { + m->bus_bcm5780[i] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_bcm5780[0], m->sbdn2 + i - 1); + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS - apicid_base = get_apicid_base(3); + apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - for(i=0;i<3;i++) - m->apicid_bcm5785[i] = apicid_base+i; + for (i = 0; i < 3; i++) + m->apicid_bcm5785[i] = apicid_base + i; } diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 091840f..4ab124d 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -39,23 +39,22 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, - 0x20202020, + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, + 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -63,66 +62,69 @@ unsigned hcdnx[] = // 0x20202020, }; - - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { - unsigned apicid_base; - struct mb_sysconf_t *m; + unsigned apicid_base; + struct mb_sysconf_t *m; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.mb = &mb_sysconf; + sysconf.mb = &mb_sysconf; - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } + /* MCP55 */ + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06, 0)); + if (dev) { + m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sysconf.sbdn + 0x06); + } - for(i=2; i<8;i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); - } - } + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(m->bus_mcp55[0], + PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); + if (dev) { + m->bus_mcp55[i] = + pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS - apicid_base = get_apicid_base(1); + apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - m->apicid_mcp55 = apicid_base+0; + m->apicid_mcp55 = apicid_base + 0; } diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index af4d6f0..f57719a 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -9,60 +9,57 @@ #include <stdlib.h> #include <cpu/amd/amdk8_sysconf.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_ck804_0; //1 - unsigned char bus_ck804_1; //2 - unsigned char bus_ck804_2; //3 - unsigned char bus_ck804_3; //4 - unsigned char bus_ck804_4; //5 - unsigned char bus_ck804_5; //6 - unsigned char bus_8131_0; //7 - unsigned char bus_8131_1; //8 - unsigned char bus_8131_2; //9 - unsigned char bus_ck804b_0;//a - unsigned char bus_ck804b_1;//b - unsigned char bus_ck804b_2;//c - unsigned char bus_ck804b_3;//d - unsigned char bus_ck804b_4;//e - unsigned char bus_ck804b_5;//f - unsigned apicid_ck804; - unsigned apicid_8131_1; - unsigned apicid_8131_2; - unsigned apicid_ck804b; +unsigned char bus_ck804_0; //1 +unsigned char bus_ck804_1; //2 +unsigned char bus_ck804_2; //3 +unsigned char bus_ck804_3; //4 +unsigned char bus_ck804_4; //5 +unsigned char bus_ck804_5; //6 +unsigned char bus_8131_0; //7 +unsigned char bus_8131_1; //8 +unsigned char bus_8131_2; //9 +unsigned char bus_ck804b_0; //a +unsigned char bus_ck804b_1; //b +unsigned char bus_ck804b_2; //c +unsigned char bus_ck804b_3; //d +unsigned char bus_ck804b_4; //e +unsigned char bus_ck804b_5; //f +unsigned apicid_ck804; +unsigned apicid_8131_1; +unsigned apicid_8131_2; +unsigned apicid_ck804b; unsigned sblk; -unsigned pci1234[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, - 0x0000ff0, +unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0 }; + unsigned hc_possible_num; unsigned sbdn; -unsigned hcdn[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, 0x20202020, 0x20202020, - 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, }; + unsigned sbdn3; unsigned sbdnb; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) @@ -70,9 +67,10 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + device_t dev; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -80,188 +78,202 @@ void get_bus_conf(void) get_sblk_pci1234(); - sbdn = (hcdn[0] & 0xff); // first byte of first chain + sbdn = (hcdn[0] & 0xff); // first byte of first chain sbdn3 = (hcdn[1] & 0xff); - sbdnb = (hcdn[2] & 0xff); // first byte of second chain + sbdnb = (hcdn[2] & 0xff); // first byte of second chain -// bus_ck804_0 = node_link_to_bus(0, sblk); +// bus_ck804_0 = node_link_to_bus(0, sblk); bus_ck804_0 = (pci1234[0] >> 16) & 0xff; - /* CK804 */ - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); - if (dev) { - bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); #if 0 - bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_2++; + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; #else - bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_5++; + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; #endif - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); - bus_ck804_1 = 2; + bus_ck804_1 = 2; #if 0 - bus_ck804_2 = 3; + bus_ck804_2 = 3; #else - bus_ck804_5 = 3; + bus_ck804_5 = 3; #endif - } + } #if 0 - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0)); - if (dev) { - bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_3++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b); - - bus_ck804_3 = bus_ck804_2+1; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0)); - if (dev) { - bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_4++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c); - - bus_ck804_4 = bus_ck804_3+1; - } - - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); - if (dev) { - bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_5++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d); - - bus_ck804_5 = bus_ck804_4+1; - } + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b, 0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0b); + + bus_ck804_3 = bus_ck804_2 + 1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c, 0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0c); + + bus_ck804_4 = bus_ck804_3 + 1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d); + + bus_ck804_5 = bus_ck804_4 + 1; + } #endif - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); - if (dev) { - bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - - bus_8131_0 = (pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - - bus_8131_1 = bus_8131_0+1; - bus_8131_2 = bus_8131_0+2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - - bus_8131_2 = bus_8131_1+1; - } - - /* CK804b */ - - if(pci1234[2] & 0xf) { //if the second cpu is installed - bus_ck804b_0 = (pci1234[2]>>16) & 0xff; + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); + } + + bus_8131_0 = (pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + + bus_8131_1 = bus_8131_0 + 1; + bus_8131_2 = bus_8131_0 + 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + + bus_8131_2 = bus_8131_1 + 1; + } + + /* CK804b */ + + if (pci1234[2] & 0xf) { //if the second cpu is installed + bus_ck804b_0 = (pci1234[2] >> 16) & 0xff; #if 0 - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0)); - if (dev) { - bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804b_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09); - - bus_ck804b_1 = bus_ck804b_0+1; - bus_ck804b_2 = bus_ck804b_0+2; - } - - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0)); - if (dev) { - bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804b_3++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b); - - bus_ck804b_2 = bus_ck804b_0+1; - bus_ck804b_3 = bus_ck804b_0+2; - } - - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0)); - if (dev) { - bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804b_4++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c); - - bus_ck804b_4 = bus_ck804b_3+1; - } - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0)); - if (dev) { - bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804b_5++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d); - - bus_ck804b_5 = bus_ck804b_4+1; - } + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0)); + if (dev) { + bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_2 = + pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x09); + + bus_ck804b_1 = bus_ck804b_0 + 1; + bus_ck804b_2 = bus_ck804b_0 + 2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b, 0)); + if (dev) { + bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_3 = + pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_3++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0b); + + bus_ck804b_2 = bus_ck804b_0 + 1; + bus_ck804b_3 = bus_ck804b_0 + 2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c, 0)); + if (dev) { + bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_4 = + pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_4++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0c); + + bus_ck804b_4 = bus_ck804b_3 + 1; + } + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d, 0)); + if (dev) { + bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_5 = + pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0d); + + bus_ck804b_5 = bus_ck804b_4 + 1; + } #endif - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0)); - if (dev) { - bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e); + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0)); + if (dev) { + bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0e); #if 1 - bus_ck804b_5 = bus_ck804b_4+1; + bus_ck804b_5 = bus_ck804b_4 + 1; #endif - } + } } - /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(4); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_ck804 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; - apicid_ck804b = apicid_base+3; + apicid_ck804 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; + apicid_ck804b = apicid_base + 3; } diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 5b16f83..0279f8f 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -31,19 +31,17 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; +unsigned char bus_mcp55[8]; //1 +unsigned apicid_mcp55; - unsigned char bus_pcix[3]; // under bus_mcp55_2 +unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -51,8 +49,8 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -62,9 +60,8 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdnb; - +unsigned sbdnb; static unsigned get_bus_conf_done = 0; @@ -74,71 +71,75 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain + sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain - for(i=0; i<8; i++) { + for (i = 0; i < 8; i++) { bus_mcp55[i] = 0; } - for(i=0; i<3; i++) { + for (i = 0; i < 3; i++) { bus_pcix[i] = 0; } - bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_mcp55[2]++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_mcp55[1] = 2; - bus_mcp55[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 ); - } + /* MCP55 */ + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0)); + if (dev) { + bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_mcp55[2]++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06); + + bus_mcp55[1] = 2; + bus_mcp55[2] = 3; + } + + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(bus_mcp55[0], + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + if (dev) { + bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_mcp55[0], sbdn + 0x0a + i - 2); } + } - if(bus_mcp55[2]) { - for(i=0;i<2; i++) { - dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); - if(dev) { - bus_pcix[0] = bus_mcp55[2]; - bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } + if (bus_mcp55[2]) { + for (i = 0; i < 2; i++) { + dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); + if (dev) { + bus_pcix[0] = bus_mcp55[2]; + bus_pcix[i + 1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); } } - + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -146,6 +147,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_mcp55 = apicid_base+0; + apicid_mcp55 = apicid_base + 0; } diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 5b16f83..0279f8f 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -31,19 +31,17 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; +unsigned char bus_mcp55[8]; //1 +unsigned apicid_mcp55; - unsigned char bus_pcix[3]; // under bus_mcp55_2 +unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -51,8 +49,8 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -62,9 +60,8 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdnb; - +unsigned sbdnb; static unsigned get_bus_conf_done = 0; @@ -74,71 +71,75 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain + sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain - for(i=0; i<8; i++) { + for (i = 0; i < 8; i++) { bus_mcp55[i] = 0; } - for(i=0; i<3; i++) { + for (i = 0; i < 3; i++) { bus_pcix[i] = 0; } - bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_mcp55[2]++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_mcp55[1] = 2; - bus_mcp55[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 ); - } + /* MCP55 */ + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0)); + if (dev) { + bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_mcp55[2]++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06); + + bus_mcp55[1] = 2; + bus_mcp55[2] = 3; + } + + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(bus_mcp55[0], + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + if (dev) { + bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_mcp55[0], sbdn + 0x0a + i - 2); } + } - if(bus_mcp55[2]) { - for(i=0;i<2; i++) { - dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); - if(dev) { - bus_pcix[0] = bus_mcp55[2]; - bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } + if (bus_mcp55[2]) { + for (i = 0; i < 2; i++) { + dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); + if (dev) { + bus_pcix[0] = bus_mcp55[2]; + bus_pcix[i + 1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); } } - + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -146,6 +147,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_mcp55 = apicid_base+0; + apicid_mcp55 = apicid_base + 0; } diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index c7b62c7..332e578 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -10,7 +10,6 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default unsigned char bus_8131_0 = 1; @@ -18,14 +17,13 @@ unsigned char bus_8131_1 = 2; unsigned char bus_8131_2 = 3; unsigned char bus_8111_0 = 1; unsigned char bus_8111_1 = 4; -unsigned apicid_8111 ; +unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -34,10 +32,10 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, +// 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -45,9 +43,8 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdn3; - +unsigned sbdn3; static unsigned get_bus_conf_done = 0; @@ -56,20 +53,21 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; @@ -77,33 +75,35 @@ void get_bus_conf(void) bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8131_0; - /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); - } - - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - } - - /* 8132-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - } - + /* 8111 */ + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:03.0, using defaults\n", + bus_8111_0); + } + + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + } + + /* 8132-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -111,7 +111,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index e390f7c..88706c0 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -19,15 +19,14 @@ unsigned char bus_8111_0 = 1; unsigned char bus_8111_1 = 4; unsigned char bus_8151_0 = 5; unsigned char bus_8151_1 = 6; -unsigned apicid_8111 ; +unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -35,8 +34,8 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -46,11 +45,10 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; + unsigned sbdn3; unsigned sbdn5; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) @@ -58,20 +56,21 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; @@ -80,43 +79,46 @@ void get_bus_conf(void) bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8131_0; - /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); - } - - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - } - - /* 8132-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - } - - /* HT chain 1 */ + /* 8111 */ + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:03.0, using defaults\n", + bus_8111_0); + } + + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + } + + /* 8132-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + } + + /* HT chain 1 */ // it is on node0, so it must be there bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8151 */ - dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0)); + /* 8151 */ + dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5 + 1, 0)); - if (dev) { - bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + if (dev) { + bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); - } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -124,7 +126,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index 6be68ad..e94c608 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -12,38 +12,36 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_ck804_0; //1 - unsigned char bus_ck804_1; //2 - unsigned char bus_ck804_2; //3 - unsigned char bus_ck804_3; //4 - unsigned char bus_ck804_4; //5 - unsigned char bus_ck804_5; //6 - unsigned char bus_8131_0; //7 - unsigned char bus_8131_1; //8 - unsigned char bus_8131_2; //9 - unsigned char bus_coproc_0; - unsigned apicid_ck804; - unsigned apicid_8131_1; - unsigned apicid_8131_2; - - -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000000, - 0x0000200, - 0x0000100, +unsigned char bus_ck804_0; //1 +unsigned char bus_ck804_1; //2 +unsigned char bus_ck804_2; //3 +unsigned char bus_ck804_3; //4 +unsigned char bus_ck804_4; //5 +unsigned char bus_ck804_5; //6 +unsigned char bus_8131_0; //7 +unsigned char bus_8131_1; //8 +unsigned char bus_8131_2; //9 +unsigned char bus_coproc_0; +unsigned apicid_ck804; +unsigned apicid_8131_1; +unsigned apicid_8131_2; + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000000, + 0x0000200, + 0x0000100, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, 0x20202020, 0x20202020, - 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -54,8 +52,6 @@ unsigned hcdnx[] = unsigned sbdn3; unsigned coprocdn; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) @@ -64,93 +60,97 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain + sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; - - /* CK804 */ - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); - if (dev) { - bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_4++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); - - bus_ck804_1 = 2; - bus_ck804_4 = 3; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); - if (dev) { - bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_5++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d); - - bus_ck804_5 = bus_ck804_4+1; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); - if (dev) { - bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - - bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - - bus_8131_1 = bus_8131_0+1; - bus_8131_2 = bus_8131_0+2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - - bus_8131_2 = bus_8131_1+1; - } - - if(sysconf.pci1234[2] & 1) { - bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; - coprocdn = (sysconf.hcdn[2] & 0xff); - } - + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + + bus_ck804_1 = 2; + bus_ck804_4 = 3; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d); + + bus_ck804_5 = bus_ck804_4 + 1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); + } + + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + + bus_8131_1 = bus_8131_0 + 1; + bus_8131_2 = bus_8131_0 + 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + + bus_8131_2 = bus_8131_1 + 1; + } + + if (sysconf.pci1234[2] & 1) { + bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; + coprocdn = (sysconf.hcdn[2] & 0xff); + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -158,7 +158,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_ck804 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_ck804 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 174632f..0ead854 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -12,24 +12,23 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_ck804_0; //1 - unsigned char bus_ck804_1; //2 - unsigned char bus_ck804_2; //3 - unsigned char bus_ck804_3; //4 - unsigned char bus_ck804_4; //5 - unsigned char bus_ck804_5; //6 - unsigned char bus_8131_0; //7 - unsigned char bus_8131_1; //8 - unsigned char bus_8131_2; //9 - unsigned apicid_ck804; - unsigned apicid_8131_1; - unsigned apicid_8131_2; - -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +unsigned char bus_ck804_0; //1 +unsigned char bus_ck804_1; //2 +unsigned char bus_ck804_2; //3 +unsigned char bus_ck804_3; //4 +unsigned char bus_ck804_4; //5 +unsigned char bus_ck804_5; //6 +unsigned char bus_8131_0; //7 +unsigned char bus_8131_1; //8 +unsigned char bus_8131_2; //9 +unsigned apicid_ck804; +unsigned apicid_8131_1; +unsigned apicid_8131_2; + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -37,8 +36,8 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -51,8 +50,6 @@ unsigned hcdnx[] = unsigned sbdn3; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) @@ -61,89 +58,92 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain + sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; - - /* CK804 */ - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); - if (dev) { - bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_4++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); - - bus_ck804_1 = 2; - bus_ck804_4 = 3; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); - if (dev) { - bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_5++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d); - - bus_ck804_5 = bus_ck804_4+1; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); - if (dev) { - bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - - bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - - bus_8131_1 = bus_8131_0+1; - bus_8131_2 = bus_8131_0+2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - - bus_8131_2 = bus_8131_1+1; - } - - + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + + bus_ck804_1 = 2; + bus_ck804_4 = 3; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d); + + bus_ck804_5 = bus_ck804_4 + 1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); + } + + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + + bus_8131_1 = bus_8131_0 + 1; + bus_8131_2 = bus_8131_0 + 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + + bus_8131_2 = bus_8131_1 + 1; + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -151,7 +151,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_ck804 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_ck804 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index abd6297..11b1bc2 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -12,43 +12,42 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_ck804_0; //1 - unsigned char bus_ck804_1; //2 - unsigned char bus_ck804_2; //3 - unsigned char bus_ck804_3; //4 - unsigned char bus_ck804_4; //5 - unsigned char bus_ck804_5; //6 - unsigned char bus_8131_0; //7 - unsigned char bus_8131_1; //8 - unsigned char bus_8131_2; //9 - unsigned char bus_ck804b_0;//a - unsigned char bus_ck804b_1;//b - unsigned char bus_ck804b_2;//c - unsigned char bus_ck804b_3;//d - unsigned char bus_ck804b_4;//e - unsigned char bus_ck804b_5;//f - unsigned apicid_ck804; - unsigned apicid_8131_1; - unsigned apicid_8131_2; - unsigned apicid_ck804b; - -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, - 0x0000ff0, +unsigned char bus_ck804_0; //1 +unsigned char bus_ck804_1; //2 +unsigned char bus_ck804_2; //3 +unsigned char bus_ck804_3; //4 +unsigned char bus_ck804_4; //5 +unsigned char bus_ck804_5; //6 +unsigned char bus_8131_0; //7 +unsigned char bus_8131_1; //8 +unsigned char bus_8131_2; //9 +unsigned char bus_ck804b_0; //a +unsigned char bus_ck804b_1; //b +unsigned char bus_ck804b_2; //c +unsigned char bus_ck804b_3; //d +unsigned char bus_ck804b_4; //e +unsigned char bus_ck804b_5; //f +unsigned apicid_ck804; +unsigned apicid_8131_1; +unsigned apicid_8131_2; +unsigned apicid_ck804b; + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, 0x20202020, 0x20202020, - 0x20202020, // 0x20202020, // 0x20202020, // 0x20202020, @@ -59,8 +58,6 @@ unsigned hcdnx[] = unsigned sbdn3; unsigned sbdnb; - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) @@ -69,92 +66,97 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; sbdn3 = (sysconf.hcdn[1] & 0xff); - sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain + sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; - /* CK804 */ - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); - if (dev) { - bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804_5++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); - - bus_ck804_1 = 2; - bus_ck804_5 = 3; - } - - dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); - if (dev) { - bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - - bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - - bus_8131_1 = bus_8131_0+1; - bus_8131_2 = bus_8131_0+2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - - bus_8131_2 = bus_8131_1+1; - } - - /* CK804b */ - - if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed - bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff; - - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0)); - if (dev) { - bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e); - bus_ck804b_5 = bus_ck804b_4+1; - } + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + + bus_ck804_1 = 2; + bus_ck804_5 = 3; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); } + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + + bus_8131_1 = bus_8131_0 + 1; + bus_8131_2 = bus_8131_0 + 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + + bus_8131_2 = bus_8131_1 + 1; + } + + /* CK804b */ + + if (sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed + bus_ck804b_0 = (sysconf.pci1234[2] >> 16) & 0xff; + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0)); + if (dev) { + bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0e); + bus_ck804b_5 = bus_ck804b_4 + 1; + } + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -162,8 +164,8 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_ck804 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; - apicid_ck804b = apicid_base+3; + apicid_ck804 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; + apicid_ck804b = apicid_base + 3; }

1 0

Patch set updated for coreboot: 6e4ed76 winent-mb6047: copy tyan/s2891 mainboard directory
by Paul Menzel 18 Oct '13

18 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3974 -gerrit commit 6e4ed76912b8dc5a81e5d11a1165dcfb5a797d61 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Oct 15 14:26:34 2013 -0500 winent-mb6047: copy tyan/s2891 mainboard directory Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/Kconfig | 56 ++++++ src/mainboard/winent/mb6047/acpi_tables.c | 190 +++++++++++++++++++ src/mainboard/winent/mb6047/cmos.layout | 98 ++++++++++ src/mainboard/winent/mb6047/devicetree.cb | 148 +++++++++++++++ src/mainboard/winent/mb6047/dsdt.asl | 282 +++++++++++++++++++++++++++++ src/mainboard/winent/mb6047/get_bus_conf.c | 164 +++++++++++++++++ src/mainboard/winent/mb6047/irq_tables.c | 168 +++++++++++++++++ src/mainboard/winent/mb6047/mptable.c | 146 +++++++++++++++ src/mainboard/winent/mb6047/resourcemap.c | 266 +++++++++++++++++++++++++++ src/mainboard/winent/mb6047/romstage.c | 148 +++++++++++++++ 10 files changed, 1666 insertions(+) diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig new file mode 100644 index 0000000..ddd7ed0 --- /dev/null +++ b/src/mainboard/winent/mb6047/Kconfig @@ -0,0 +1,56 @@ +if BOARD_TYAN_S2891 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select SERIAL_CPU_INIT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default tyan/s2891 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config MAINBOARD_PART_NUMBER + string + default "S2891" + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 11 + +endif # BOARD_TYAN_S2891 diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c new file mode 100644 index 0000000..42d9152 --- /dev/null +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -0,0 +1,190 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include "northbridge/amd/amdk8/acpi.h" +#include <cpu/amd/model_fxx_powernow.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); +#endif + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); + return current; +} diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout new file mode 100644 index 0000000..924934c --- /dev/null +++ b/src/mainboard/winent/mb6047/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb new file mode 100644 index 0000000..3d8c65e --- /dev/null +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -0,0 +1,148 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x10f1 0x2891 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 7.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end + device pci 9.1 on end + end + device pci 1.1 on end + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 off end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 off end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 on end # hard_reset + # end +end diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl new file mode 100644 index 0000000..1c8680b --- /dev/null +++ b/src/mainboard/winent/mb6047/dsdt.asl @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + }) + } + } + } +} diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c new file mode 100644 index 0000000..e94c608 --- /dev/null +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -0,0 +1,164 @@ +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +//busnum is default +unsigned char bus_ck804_0; //1 +unsigned char bus_ck804_1; //2 +unsigned char bus_ck804_2; //3 +unsigned char bus_ck804_3; //4 +unsigned char bus_ck804_4; //5 +unsigned char bus_ck804_5; //6 +unsigned char bus_8131_0; //7 +unsigned char bus_8131_1; //8 +unsigned char bus_8131_2; //9 +unsigned char bus_coproc_0; +unsigned apicid_ck804; +unsigned apicid_8131_1; +unsigned apicid_8131_2; + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000000, + 0x0000200, + 0x0000100, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, + 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +}; + +unsigned sbdn3; +unsigned coprocdn; + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + unsigned sbdn; + + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; //do it only once + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain + + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; + + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + + bus_ck804_1 = 2; + bus_ck804_4 = 3; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d); + + bus_ck804_5 = bus_ck804_4 + 1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); + } + + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); + + bus_8131_1 = bus_8131_0 + 1; + bus_8131_2 = bus_8131_0 + 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); + + bus_8131_2 = bus_8131_1 + 1; + } + + if (sysconf.pci1234[2] & 1) { + bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; + coprocdn = (sysconf.hcdn[2] & 0xff); + } + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_ck804 = apicid_base + 0; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; +} diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c new file mode 100644 index 0000000..d584dbb --- /dev/null +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -0,0 +1,168 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern unsigned char bus_ck804_0; //1 +extern unsigned char bus_ck804_1; //2 +extern unsigned char bus_ck804_2; //3 +extern unsigned char bus_ck804_3; //4 +extern unsigned char bus_ck804_4; //5 +extern unsigned char bus_ck804_5; //6 +extern unsigned char bus_8131_0; //7 +extern unsigned char bus_8131_1; //8 +extern unsigned char bus_8131_2; //9 +extern unsigned char bus_coproc_0; + +extern unsigned sbdn3; +extern unsigned coprocdn; + + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + unsigned sbdn; + + uint8_t sum=0; + int i; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_ck804_0; + pirq->rtr_devfn = ((sbdn+9)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; +//pcix bridge + write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; +//co processor + if(sysconf.pci1234[2] & 1) { + write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } + +#if 0 +//smbus + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//usb + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//audio + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//nic + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//Slot1 PCIE x16 + write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); + pirq_info++; slot_num++; + +//firewire + write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//Slot2 pci + write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); + pirq_info++; slot_num++; +//Slot3 PCIE x16 + write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); + pirq_info++; slot_num++; + +//Slot4 PCIX + write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); + pirq_info++; slot_num++; + +//Slot5 PCIX + write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); + pirq_info++; slot_num++; + +//Slot6 PCIX + write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); + pirq_info++; slot_num++; +#endif + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long) pirq_info; + +} diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c new file mode 100644 index 0000000..cb49434 --- /dev/null +++ b/src/mainboard/winent/mb6047/mptable.c @@ -0,0 +1,146 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern unsigned char bus_ck804_0; //1 +extern unsigned char bus_ck804_1; //2 +extern unsigned char bus_ck804_2; //3 +extern unsigned char bus_ck804_3; //4 +extern unsigned char bus_ck804_4; //5 +extern unsigned char bus_ck804_5; //6 +extern unsigned char bus_8131_0; //7 +extern unsigned char bus_8131_1; //8 +extern unsigned char bus_8131_2; //9 +extern unsigned apicid_ck804; +extern unsigned apicid_8131_1; +extern unsigned apicid_8131_2; + +extern unsigned sbdn3; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int i, bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping*/ + + dword = 0x0120d218; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x12008a00; + pci_write_config32(dev, 0x80, dword); + + dword = 0x0000007d; + pci_write_config32(dev, 0x84, dword); + + } + + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + } + + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1); + +// Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 + +// Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 + +// Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 + +// Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 + +// Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 + +//Slot PCIE x16 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); + } + +//Slot PCIE x4 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); + } + +//Onboard ati + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 + +//Channel B of 8131 + + +//Onboard Broadcom NIC + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 + } + +//Channel A of 8131 + +//Slot 4 PCIX 133/100/66 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 + } + +//Slot 3 PCIX 133/100/66 SoDIMM PCI + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 + } + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/winent/mb6047/resourcemap.c b/src/mainboard/winent/mb6047/resourcemap.c new file mode 100644 index 0000000..d76f1d6 --- /dev/null +++ b/src/mainboard/winent/mb6047/resourcemap.c @@ -0,0 +1,266 @@ +/* + * Tyan S2891 needs a different resource map + * + */ + +static void setup_s2891_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} + diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c new file mode 100644 index 0000000..9cd3a4a --- /dev/null +++ b/src/mainboard/winent/mb6047/romstage.c @@ -0,0 +1,148 @@ +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/nvidia/ck804/early_smbus.h" +#include "northbridge/amd/amdk8/raminit.h" +#include "lib/delay.c" +#include "cpu/x86/lapic.h" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627hf/early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void memreset_setup(void) { } +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + uint32_t dword; + uint8_t byte; + + /* subject decoding*/ + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1<<0) | (1<<1); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + +#if 1 + /* s2891 has onboard LPC port 80 */ + /*Hope I can enable port 80 here + It will decode port 80 to LPC, If you are using PCI post code you can not do this */ + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); +#endif +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, +#endif + }; + + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8]; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + sio_setup(); + } + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx); + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_s2891_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + needs_reset |= ht_setup_chains_x(); + needs_reset |= ck804_early_setup_x(); + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); +#endif + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + print_pci_devices(); + dump_pci_devices(); +#endif + + post_cache_as_ram(); +}

1 0

Patch set updated for coreboot: 5014e20 winent-mb6047: initial board port
by Paul Menzel 18 Oct '13

18 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3975 -gerrit commit 5014e20e0656c1a074c4d62c745804a196273ae4 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Oct 15 16:45:51 2013 -0500 winent-mb6047: initial board port Thanks to WIN Enterprises for providing boards. Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/Kconfig | 4 + src/mainboard/winent/mb6047/Kconfig | 26 ++- src/mainboard/winent/mb6047/acpi_tables.c | 16 -- src/mainboard/winent/mb6047/devicetree.cb | 45 ++--- src/mainboard/winent/mb6047/dsdt.asl | 190 +++++++-------------- src/mainboard/winent/mb6047/get_bus_conf.c | 40 ----- src/mainboard/winent/mb6047/irq_tables.c | 17 -- src/mainboard/winent/mb6047/mptable.c | 42 ----- src/mainboard/winent/mb6047/resourcemap.c | 266 ----------------------------- src/mainboard/winent/mb6047/romstage.c | 45 +++-- 10 files changed, 124 insertions(+), 567 deletions(-) diff --git a/src/mainboard/winent/Kconfig b/src/mainboard/winent/Kconfig index 4c13a82..28c3360 100644 --- a/src/mainboard/winent/Kconfig +++ b/src/mainboard/winent/Kconfig @@ -21,11 +21,15 @@ if VENDOR_WINENT choice prompt "Mainboard model" +config BOARD_WINENT_MB6047 + bool "MB6047" + config BOARD_WINENT_PL6064 bool "PL6064" endchoice +source "src/mainboard/winent/mb6047/Kconfig" source "src/mainboard/winent/pl6064/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index ddd7ed0..c7b09d2 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -1,4 +1,4 @@ -if BOARD_TYAN_S2891 +if BOARD_WINENT_MB6047 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -6,8 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 - select SOUTHBRIDGE_AMD_AMD8131 - select SUPERIO_WINBOND_W83627HF + select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -16,10 +15,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select CK804_USE_NIC + select CK804_USE_ACI + select SET_FIDVID config MAINBOARD_DIR string - default tyan/s2891 + default winent/mb6047 config APIC_ID_OFFSET hex @@ -31,7 +33,7 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "S2891" + default "MB6047" config MAX_CPUS int @@ -53,4 +55,16 @@ config IRQ_SLOT_COUNT int default 11 -endif # BOARD_TYAN_S2891 +config CK804_PCI_E_X + int + default 0 + +config VGA_BIOS_ID + string + default "126f,0720" + +config VGA_BIOS_FILE + string + default "DM22383.ROM" + +endif # BOARD_WINENT_MB6047 diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 42d9152..1b59fbb 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -30,7 +30,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { - unsigned long apic_addr; device_t dev; struct resource *res; @@ -53,21 +52,6 @@ unsigned long acpi_fill_madt(unsigned long current) pci_write_config32(dev, 0x84, 0x0000007d); #endif - /* Write AMD 8131 two IOAPICs. */ - dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); - } - - dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); - } - /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 3d8c65e..09a062e 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -5,13 +5,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x10f1 0x2891 inherit + subsystemid 0x10de 0xcb84 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O + chip superio/winbond/w83627thg # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -35,20 +35,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Consumer IR - io 0x60 = 0x100 - end - device pnp 2e.7 off # Game port, MIDI, GPIO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI - device pnp 2e.b off # Hardware monitor + device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 - irq 0x70 = 5 + irq 0x70 = 0 end end end @@ -97,38 +91,27 @@ chip northbridge/amd/amdk8/root_complex # Root complex # end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI + device pci 4.0 on end # ACI device pci 4.1 off end # MCI device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 7.0 on end + # device pci 6.0 on end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0 register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide1_enable" = "0" register "sata0_enable" = "1" register "sata1_enable" = "1" end end device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end - device pci 9.1 on end - end - device pci 1.1 on end - end - end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl index 1c8680b..aa04d81 100644 --- a/src/mainboard/winent/mb6047/dsdt.asl +++ b/src/mainboard/winent/mb6047/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { - #include "northbridge/amd/amdk8/util.asl" + #include "northbridge/amd/amdk8/util.asl" /* For now only define 2 power states: * - S0 which is fully on @@ -32,7 +32,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) * Any others would involve declaring the wake up methods. */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) - Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) + + Name (PICM, 0x00) + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } /* Root of the bus hierarchy */ Scope (\_SB) @@ -83,53 +88,80 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (Local3) } + #include "southbridge/nvidia/ck804/acpi/ck804.asl" + /* PCI Routing Table */ Name (_PRT, Package () { - /* Since source is 0, index is IRQ. */ - /* in ABCD, A=0, B=1, C=2, D=3 */ - /* SlotFFFF, ABCD, source, index */ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 }, + Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 }, }) Device (PCIL) { Name (_ADR, 0x00090000) Name (_UID, 0x00) - Name (_BBN, 0x01) Name (_PRT, Package () { - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + /* onboard SM720 VGA */ + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, }) } - /* 2:00 PCIe x16 SB IRQ 18 */ - Device (PE16) + Device (PEX0) { Name (_ADR, 0x000e0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, }) } - /* 2:00 PCIe x4 SB IRQ 17 */ - Device (PE4) + Device (PEX1) { - Name (_ADR, 0x000e0000) + Name (_ADR, 0x000d0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x000c0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x000b0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, }) } @@ -172,110 +204,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (TMP) } } - - /* Parallel port */ - Device (LP0) - { - Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - FixedIO (0x0378, 0x10) - IRQNoFlags () {7} - }) - Return (TMP) - } - } - - /* Floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - FixedIO (0x03F0, 0x08) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - } - } - - /* AMD 8131 PCI-X tunnel */ - Device (PCI2) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_UID, 0x00) - Name (_BBN, 0x40) - - /* There is no _PRT Here because I don't know what to - * put in it. Since the 8131 has its own APIC, it - * isn't wired to other IRQs. */ - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - }) - /* Methods bellow use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - \_SB.GXXX(node, link) - */ - Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) - Return (Local3) - } - - /* Channel A PCIX 133 */ - Device (PCXF) - { - Name (_ADR, 0x00000000) - Name (_UID, 0x00) - Name (_BBN, 0x41) - Name (_PRT, Package () { - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ - Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, - }) - } - - /* Channel B PCIX 100 */ - Device (PCXS) /* Onboard NIC */ - { - Name (_ADR, 0x00010000) - Name (_UID, 0x00) - Name (_BBN, 0x42) - Name (_PRT, Package () { - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, - Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, - Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, - }) } } } diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index e94c608..9d9f154 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -18,13 +18,7 @@ unsigned char bus_ck804_2; //3 unsigned char bus_ck804_3; //4 unsigned char bus_ck804_4; //5 unsigned char bus_ck804_5; //6 -unsigned char bus_8131_0; //7 -unsigned char bus_8131_1; //8 -unsigned char bus_8131_2; //9 -unsigned char bus_coproc_0; unsigned apicid_ck804; -unsigned apicid_8131_1; -unsigned apicid_8131_2; unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail @@ -120,38 +114,6 @@ void get_bus_conf(void) sbdn + 0x0e); } - bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); - - bus_8131_1 = bus_8131_0 + 1; - bus_8131_2 = bus_8131_0 + 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); - - bus_8131_2 = bus_8131_1 + 1; - } - - if (sysconf.pci1234[2] & 1) { - bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; - coprocdn = (sysconf.hcdn[2] & 0xff); - } - /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); @@ -159,6 +121,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_ck804 = apicid_base + 0; - apicid_8131_1 = apicid_base + 1; - apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c index d584dbb..8b0c18e 100644 --- a/src/mainboard/winent/mb6047/irq_tables.c +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -36,15 +36,6 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 -extern unsigned char bus_coproc_0; - -extern unsigned sbdn3; -extern unsigned coprocdn; - - unsigned long write_pirq_routing_table(unsigned long addr) { @@ -91,14 +82,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; -//pcix bridge - write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; -//co processor - if(sysconf.pci1234[2] & 1) { - write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - } #if 0 //smbus diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index cb49434..fa74553 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -11,14 +11,8 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 extern unsigned apicid_ck804; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2; -extern unsigned sbdn3; static void *smp_write_config_table(void *v) { @@ -60,22 +54,6 @@ static void *smp_write_config_table(void *v) dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); - - } - - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } } } @@ -110,26 +88,6 @@ static void *smp_write_config_table(void *v) //Onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 -//Channel B of 8131 - - -//Onboard Broadcom NIC - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 - } - -//Channel A of 8131 - -//Slot 4 PCIX 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 - } - -//Slot 3 PCIX 133/100/66 SoDIMM PCI - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 - } - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ diff --git a/src/mainboard/winent/mb6047/resourcemap.c b/src/mainboard/winent/mb6047/resourcemap.c deleted file mode 100644 index d76f1d6..0000000 --- a/src/mainboard/winent/mb6047/resourcemap.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Tyan S2891 needs a different resource map - * - */ - -static void setup_s2891_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} - diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 9cd3a4a..8049bcb 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -16,12 +16,12 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include "superio/winbond/w83627thg/early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -35,12 +35,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -59,24 +61,16 @@ static void sio_setup(void) dword |= (1<<0) | (1<<1); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); -#if 1 - /* s2891 has onboard LPC port 80 */ - /*Hope I can enable port 80 here - It will decode port 80 to LPC, If you are using PCI post code you can not do this */ - dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); -#endif } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, 0, 0, 0, + DIMM1, 0, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, #endif }; @@ -96,16 +90,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_s2891_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); @@ -117,6 +109,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); #endif +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { + msr_t msr; + /* Read FIDVID_STATUS */ + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + } +#endif + needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) {

1 0

New patch to review for coreboot: 025ede6 Build without ChromeOS
by Kyösti Mälkki 17 Oct '13

17 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3978 -gerrit commit 025ede6e52ff6dabbf819ea9c88ffcd038ba0338 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a564608..a707717 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM help Enable ChromeOS specific features like the GPIO sub table in

1 0

New patch to review for coreboot: 6e66b64 Add option to disable ChromeOS
by Kyösti Mälkki 17 Oct '13

17 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3977 -gerrit commit 6e66b64e70800831002fd0fc520e90822e13ed2c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:25 2013 +0300 Add option to disable ChromeOS Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/pit/Kconfig | 2 +- src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/intel/wtm2/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- src/vendorcode/google/chromeos/Kconfig | 20 ++++++++++++-------- 12 files changed, 23 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index e9ad6ef..78c998a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index b74c604..d1e809e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 191e856..d8a4e7a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 89ffb5b..ae6e693 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select BOARD_ROMSIZE_KB_4096 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_INIT_TIMER diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 91bd66d..279132d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select DRIVER_TI_TPS65090 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index a316277..7ee8fd4 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index cf4a901..e4f5351 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index fd98485..01082d4 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select GFXUMA - #select CHROMEOS + #select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT config MAINBOARD_DIR diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index dfee8ab..16b671d 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 91dc3b6..032b4b5 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select BOARD_ROMSIZE_KB_8192 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select GFXUMA diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index f4f8e4d..e1e0cfa 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select BOARD_ROMSIZE_KB_8192 - select CHROMEOS + select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 select GFXUMA select HAVE_ACPI_RESUME diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index d5ca212..a564608 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -16,17 +16,22 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config MAINBOARD_HAS_CHROMEOS + def_bool n + +menu "ChromeOS" + depends on MAINBOARD_HAS_CHROMEOS + config CHROMEOS - bool - default n + bool "Build for ChromeOS" + default y select TPM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build. -menu "ChromeOS" - depends on CHROMEOS +if CHROMEOS config VBNV_OFFSET hex @@ -66,12 +71,9 @@ config FLASHMAP_OFFSET help Offset of flash map in firmware image -endmenu - config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." default n - depends on CHROMEOS help Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage and boot loader. @@ -111,8 +113,10 @@ config VBOOT_RAMSTAGE_INDEX config NO_TPM_RESUME bool default n - depends on CHROMEOS help On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume. + +endif +endmenu

1 0

Patch merged into coreboot/master: cd9abf9 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
by gerrit＠coreboot.org 17 Oct '13

17 Oct '13

the following patch was just integrated into master: commit cd9abf95e7fe3d67f02e5e0197efa2688db83d22 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3896 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/3896 for details. -gerrit

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Patch merged into coreboot/master: c2a8031 libpayload/sample: Use settings from .xcompile file to build.
by gerrit＠coreboot.org 17 Oct '13

17 Oct '13

the following patch was just integrated into master: commit c2a8031a5eb8ed22ab6f906e44445af1c9487361 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Oct 7 16:27:01 2013 +0800 libpayload/sample: Use settings from .xcompile file to build. It is for crossgcc. Change-Id: Ia1d676adfea340b6b80858215459491c9338d614 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3955 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/3955 for details. -gerrit

1 0

New patch to review for coreboot: 2ea776a dmp/vortex86ex: Initialize I2C controller base address/IRQ
by Andrew Wu 16 Oct '13

16 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit 2ea776ae7029f7aeedc8a5edcc4ce269ae2f00c0 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 16 13:08:30 2013 +0800 dmp/vortex86ex: Initialize I2C controller base address/IRQ Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 15 +++++++++++++++ src/southbridge/dmp/vortex86ex/southbridge.h | 1 + 2 files changed, 16 insertions(+) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d8914c0..99a5a69 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = { #define PIDE_IRQ 5 #define SPI1_IRQ 10 +#define I2C0_IRQ 10 #define MOTOR_IRQ 11 /* RT0-3 IRQs. */ @@ -89,6 +90,9 @@ static const unsigned char irq_to_int_routing[16] = { #define LPT_PDMAS 0 #define LPT_DREQS 0 +/* internal I2C */ +#define I2C_BASE 0xfb00 + /* Post codes */ #define POST_KBD_FW_UPLOAD 0x06 #define POST_KBD_CHK_READY 0x07 @@ -418,6 +422,16 @@ static void ex_sb_uart_init(struct device *dev) //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0); } +static void i2c_init(struct device *dev) +{ + u8 mapped_irq = irq_to_int_routing[I2C0_IRQ]; + u32 cfg = 0; + cfg |= 1 << 31; // UE = enabled. + cfg |= (mapped_irq << 16); // IIRT0. + cfg |= I2C_BASE; // UIOA. + pci_write_config32(dev, SB_REG_II2CCR, cfg); +} + static int get_rtc_update_in_progress(void) { if (cmos_read(RTC_REG_A) & RTC_UIP) @@ -566,6 +580,7 @@ static void southbridge_init(struct device *dev) if (dev->device == 0x6011) { ex_sb_gpio_init(dev); ex_sb_uart_init(dev); + i2c_init(dev); } pci_routing_fixup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 0cc28fa..316d30a 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -36,6 +36,7 @@ #define SB_REG_IPFCR 0xc0 #define SB_REG_FRWPR 0xc4 #define SB_REG_STRAP 0xce +#define SB_REG_II2CCR 0xd4 #define SB1 PCI_DEV(0, 7, 1) #define SB1_REG_EXT_PIRQ_ROUTE2 0xb4

1 0

New patch to review for coreboot: d101539 winent-mb6047: initial board port
by Jonathan A. Kollasch 15 Oct '13

15 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3975 -gerrit commit d1015396d0c17032c0ef419d04b77e0fe0b82f72 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Oct 15 16:45:51 2013 -0500 winent-mb6047: initial board port Thanks to WIN Enterprises for providing boards. Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/Kconfig | 4 + src/mainboard/winent/mb6047/Kconfig | 26 ++- src/mainboard/winent/mb6047/acpi_tables.c | 16 -- src/mainboard/winent/mb6047/devicetree.cb | 45 ++--- src/mainboard/winent/mb6047/dsdt.asl | 190 +++++++-------------- src/mainboard/winent/mb6047/get_bus_conf.c | 39 ----- src/mainboard/winent/mb6047/irq_tables.c | 17 -- src/mainboard/winent/mb6047/mptable.c | 42 ----- src/mainboard/winent/mb6047/resourcemap.c | 266 ----------------------------- src/mainboard/winent/mb6047/romstage.c | 45 +++-- 10 files changed, 124 insertions(+), 566 deletions(-) diff --git a/src/mainboard/winent/Kconfig b/src/mainboard/winent/Kconfig index 4c13a82..28c3360 100644 --- a/src/mainboard/winent/Kconfig +++ b/src/mainboard/winent/Kconfig @@ -21,11 +21,15 @@ if VENDOR_WINENT choice prompt "Mainboard model" +config BOARD_WINENT_MB6047 + bool "MB6047" + config BOARD_WINENT_PL6064 bool "PL6064" endchoice +source "src/mainboard/winent/mb6047/Kconfig" source "src/mainboard/winent/pl6064/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index ddd7ed0..c7b09d2 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -1,4 +1,4 @@ -if BOARD_TYAN_S2891 +if BOARD_WINENT_MB6047 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -6,8 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 - select SOUTHBRIDGE_AMD_AMD8131 - select SUPERIO_WINBOND_W83627HF + select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -16,10 +15,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select CK804_USE_NIC + select CK804_USE_ACI + select SET_FIDVID config MAINBOARD_DIR string - default tyan/s2891 + default winent/mb6047 config APIC_ID_OFFSET hex @@ -31,7 +33,7 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "S2891" + default "MB6047" config MAX_CPUS int @@ -53,4 +55,16 @@ config IRQ_SLOT_COUNT int default 11 -endif # BOARD_TYAN_S2891 +config CK804_PCI_E_X + int + default 0 + +config VGA_BIOS_ID + string + default "126f,0720" + +config VGA_BIOS_FILE + string + default "DM22383.ROM" + +endif # BOARD_WINENT_MB6047 diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 42d9152..1b59fbb 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -30,7 +30,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { - unsigned long apic_addr; device_t dev; struct resource *res; @@ -53,21 +52,6 @@ unsigned long acpi_fill_madt(unsigned long current) pci_write_config32(dev, 0x84, 0x0000007d); #endif - /* Write AMD 8131 two IOAPICs. */ - dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); - } - - dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); - } - /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 3d8c65e..09a062e 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -5,13 +5,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x10f1 0x2891 inherit + subsystemid 0x10de 0xcb84 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O + chip superio/winbond/w83627thg # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -35,20 +35,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Consumer IR - io 0x60 = 0x100 - end - device pnp 2e.7 off # Game port, MIDI, GPIO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI - device pnp 2e.b off # Hardware monitor + device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 - irq 0x70 = 5 + irq 0x70 = 0 end end end @@ -97,38 +91,27 @@ chip northbridge/amd/amdk8/root_complex # Root complex # end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI + device pci 4.0 on end # ACI device pci 4.1 off end # MCI device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 7.0 on end + # device pci 6.0 on end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0 register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide1_enable" = "0" register "sata0_enable" = "1" register "sata1_enable" = "1" end end device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end - device pci 9.1 on end - end - device pci 1.1 on end - end - end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl index 1c8680b..aa04d81 100644 --- a/src/mainboard/winent/mb6047/dsdt.asl +++ b/src/mainboard/winent/mb6047/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { - #include "northbridge/amd/amdk8/util.asl" + #include "northbridge/amd/amdk8/util.asl" /* For now only define 2 power states: * - S0 which is fully on @@ -32,7 +32,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) * Any others would involve declaring the wake up methods. */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) - Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) + + Name (PICM, 0x00) + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } /* Root of the bus hierarchy */ Scope (\_SB) @@ -83,53 +88,80 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (Local3) } + #include "southbridge/nvidia/ck804/acpi/ck804.asl" + /* PCI Routing Table */ Name (_PRT, Package () { - /* Since source is 0, index is IRQ. */ - /* in ABCD, A=0, B=1, C=2, D=3 */ - /* SlotFFFF, ABCD, source, index */ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 }, + Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 }, }) Device (PCIL) { Name (_ADR, 0x00090000) Name (_UID, 0x00) - Name (_BBN, 0x01) Name (_PRT, Package () { - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + /* onboard SM720 VGA */ + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, }) } - /* 2:00 PCIe x16 SB IRQ 18 */ - Device (PE16) + Device (PEX0) { Name (_ADR, 0x000e0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, }) } - /* 2:00 PCIe x4 SB IRQ 17 */ - Device (PE4) + Device (PEX1) { - Name (_ADR, 0x000e0000) + Name (_ADR, 0x000d0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x000c0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x000b0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, }) } @@ -172,110 +204,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (TMP) } } - - /* Parallel port */ - Device (LP0) - { - Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - FixedIO (0x0378, 0x10) - IRQNoFlags () {7} - }) - Return (TMP) - } - } - - /* Floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - FixedIO (0x03F0, 0x08) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - } - } - - /* AMD 8131 PCI-X tunnel */ - Device (PCI2) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_UID, 0x00) - Name (_BBN, 0x40) - - /* There is no _PRT Here because I don't know what to - * put in it. Since the 8131 has its own APIC, it - * isn't wired to other IRQs. */ - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - }) - /* Methods bellow use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - \_SB.GXXX(node, link) - */ - Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) - Return (Local3) - } - - /* Channel A PCIX 133 */ - Device (PCXF) - { - Name (_ADR, 0x00000000) - Name (_UID, 0x00) - Name (_BBN, 0x41) - Name (_PRT, Package () { - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ - Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, - }) - } - - /* Channel B PCIX 100 */ - Device (PCXS) /* Onboard NIC */ - { - Name (_ADR, 0x00010000) - Name (_UID, 0x00) - Name (_BBN, 0x42) - Name (_PRT, Package () { - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, - Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, - Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, - }) } } } diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 6be68ad..3b20fb6 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -18,13 +18,7 @@ unsigned char bus_ck804_3; //4 unsigned char bus_ck804_4; //5 unsigned char bus_ck804_5; //6 - unsigned char bus_8131_0; //7 - unsigned char bus_8131_1; //8 - unsigned char bus_8131_2; //9 - unsigned char bus_coproc_0; unsigned apicid_ck804; - unsigned apicid_8131_1; - unsigned apicid_8131_2; unsigned pci1234x[] = @@ -121,37 +115,6 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); } - bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); - - bus_8131_1 = bus_8131_0+1; - bus_8131_2 = bus_8131_0+2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); - - bus_8131_2 = bus_8131_1+1; - } - - if(sysconf.pci1234[2] & 1) { - bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; - coprocdn = (sysconf.hcdn[2] & 0xff); - } - - /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); @@ -159,6 +122,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_ck804 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; } diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c index d584dbb..8b0c18e 100644 --- a/src/mainboard/winent/mb6047/irq_tables.c +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -36,15 +36,6 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 -extern unsigned char bus_coproc_0; - -extern unsigned sbdn3; -extern unsigned coprocdn; - - unsigned long write_pirq_routing_table(unsigned long addr) { @@ -91,14 +82,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; -//pcix bridge - write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; -//co processor - if(sysconf.pci1234[2] & 1) { - write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - } #if 0 //smbus diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index cb49434..fa74553 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -11,14 +11,8 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 extern unsigned apicid_ck804; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2; -extern unsigned sbdn3; static void *smp_write_config_table(void *v) { @@ -60,22 +54,6 @@ static void *smp_write_config_table(void *v) dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); - - } - - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } } } @@ -110,26 +88,6 @@ static void *smp_write_config_table(void *v) //Onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 -//Channel B of 8131 - - -//Onboard Broadcom NIC - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 - } - -//Channel A of 8131 - -//Slot 4 PCIX 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 - } - -//Slot 3 PCIX 133/100/66 SoDIMM PCI - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 - } - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ diff --git a/src/mainboard/winent/mb6047/resourcemap.c b/src/mainboard/winent/mb6047/resourcemap.c deleted file mode 100644 index d76f1d6..0000000 --- a/src/mainboard/winent/mb6047/resourcemap.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Tyan S2891 needs a different resource map - * - */ - -static void setup_s2891_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} - diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 9cd3a4a..8049bcb 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -16,12 +16,12 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include "superio/winbond/w83627thg/early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -35,12 +35,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -59,24 +61,16 @@ static void sio_setup(void) dword |= (1<<0) | (1<<1); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); -#if 1 - /* s2891 has onboard LPC port 80 */ - /*Hope I can enable port 80 here - It will decode port 80 to LPC, If you are using PCI post code you can not do this */ - dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); -#endif } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, 0, 0, 0, + DIMM1, 0, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, #endif }; @@ -96,16 +90,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_s2891_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); @@ -117,6 +109,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); #endif +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { + msr_t msr; + /* Read FIDVID_STATUS */ + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + } +#endif + needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) {

1 0

New patch to review for coreboot: 2fee949 winent-mb6047: copy tyan/s2891 mainboard directory
by Jonathan A. Kollasch 15 Oct '13

15 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3974 -gerrit commit 2fee949d5e7ec9d5e185b242656e15acc59b17e0 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Oct 15 14:26:34 2013 -0500 winent-mb6047: copy tyan/s2891 mainboard directory Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/Kconfig | 56 ++++++ src/mainboard/winent/mb6047/acpi_tables.c | 190 +++++++++++++++++++ src/mainboard/winent/mb6047/cmos.layout | 98 ++++++++++ src/mainboard/winent/mb6047/devicetree.cb | 148 +++++++++++++++ src/mainboard/winent/mb6047/dsdt.asl | 282 +++++++++++++++++++++++++++++ src/mainboard/winent/mb6047/get_bus_conf.c | 164 +++++++++++++++++ src/mainboard/winent/mb6047/irq_tables.c | 168 +++++++++++++++++ src/mainboard/winent/mb6047/mptable.c | 146 +++++++++++++++ src/mainboard/winent/mb6047/resourcemap.c | 266 +++++++++++++++++++++++++++ src/mainboard/winent/mb6047/romstage.c | 148 +++++++++++++++ 10 files changed, 1666 insertions(+) diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig new file mode 100644 index 0000000..ddd7ed0 --- /dev/null +++ b/src/mainboard/winent/mb6047/Kconfig @@ -0,0 +1,56 @@ +if BOARD_TYAN_S2891 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select SERIAL_CPU_INIT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default tyan/s2891 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config MAINBOARD_PART_NUMBER + string + default "S2891" + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 11 + +endif # BOARD_TYAN_S2891 diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c new file mode 100644 index 0000000..42d9152 --- /dev/null +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -0,0 +1,190 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include "northbridge/amd/amdk8/acpi.h" +#include <cpu/amd/model_fxx_powernow.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); +#endif + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); + return current; +} diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout new file mode 100644 index 0000000..924934c --- /dev/null +++ b/src/mainboard/winent/mb6047/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb new file mode 100644 index 0000000..3d8c65e --- /dev/null +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -0,0 +1,148 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x10f1 0x2891 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 7.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end + device pci 9.1 on end + end + device pci 1.1 on end + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 off end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 off end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 on end # hard_reset + # end +end diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl new file mode 100644 index 0000000..1c8680b --- /dev/null +++ b/src/mainboard/winent/mb6047/dsdt.asl @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + }) + } + } + } +} diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c new file mode 100644 index 0000000..6be68ad --- /dev/null +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -0,0 +1,164 @@ +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +//busnum is default + unsigned char bus_ck804_0; //1 + unsigned char bus_ck804_1; //2 + unsigned char bus_ck804_2; //3 + unsigned char bus_ck804_3; //4 + unsigned char bus_ck804_4; //5 + unsigned char bus_ck804_5; //6 + unsigned char bus_8131_0; //7 + unsigned char bus_8131_1; //8 + unsigned char bus_8131_2; //9 + unsigned char bus_coproc_0; + unsigned apicid_ck804; + unsigned apicid_8131_1; + unsigned apicid_8131_2; + + +unsigned pci1234x[] = +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000000, + 0x0000200, + 0x0000100, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; +unsigned hcdnx[] = +{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, + 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +}; + +unsigned sbdn3; +unsigned coprocdn; + + + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + unsigned sbdn; + + device_t dev; + int i; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain + + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; + + + /* CK804 */ + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); + if (dev) { + bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); + + bus_ck804_1 = 2; + bus_ck804_4 = 3; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d); + + bus_ck804_5 = bus_ck804_4+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); + if (dev) { + bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); + } + + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_8131_2++; + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); + + bus_8131_1 = bus_8131_0+1; + bus_8131_2 = bus_8131_0+2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); + + bus_8131_2 = bus_8131_1+1; + } + + if(sysconf.pci1234[2] & 1) { + bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; + coprocdn = (sysconf.hcdn[2] & 0xff); + } + + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_ck804 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2; +} diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c new file mode 100644 index 0000000..d584dbb --- /dev/null +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -0,0 +1,168 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern unsigned char bus_ck804_0; //1 +extern unsigned char bus_ck804_1; //2 +extern unsigned char bus_ck804_2; //3 +extern unsigned char bus_ck804_3; //4 +extern unsigned char bus_ck804_4; //5 +extern unsigned char bus_ck804_5; //6 +extern unsigned char bus_8131_0; //7 +extern unsigned char bus_8131_1; //8 +extern unsigned char bus_8131_2; //9 +extern unsigned char bus_coproc_0; + +extern unsigned sbdn3; +extern unsigned coprocdn; + + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + unsigned sbdn; + + uint8_t sum=0; + int i; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_ck804_0; + pirq->rtr_devfn = ((sbdn+9)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; +//pcix bridge + write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; +//co processor + if(sysconf.pci1234[2] & 1) { + write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } + +#if 0 +//smbus + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//usb + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//audio + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//sata + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; +//nic + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//Slot1 PCIE x16 + write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); + pirq_info++; slot_num++; + +//firewire + write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; + +//Slot2 pci + write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); + pirq_info++; slot_num++; +//Slot3 PCIE x16 + write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); + pirq_info++; slot_num++; + +//Slot4 PCIX + write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); + pirq_info++; slot_num++; + +//Slot5 PCIX + write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); + pirq_info++; slot_num++; + +//Slot6 PCIX + write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); + pirq_info++; slot_num++; +#endif + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long) pirq_info; + +} diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c new file mode 100644 index 0000000..cb49434 --- /dev/null +++ b/src/mainboard/winent/mb6047/mptable.c @@ -0,0 +1,146 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern unsigned char bus_ck804_0; //1 +extern unsigned char bus_ck804_1; //2 +extern unsigned char bus_ck804_2; //3 +extern unsigned char bus_ck804_3; //4 +extern unsigned char bus_ck804_4; //5 +extern unsigned char bus_ck804_5; //6 +extern unsigned char bus_8131_0; //7 +extern unsigned char bus_8131_1; //8 +extern unsigned char bus_8131_2; //9 +extern unsigned apicid_ck804; +extern unsigned apicid_8131_1; +extern unsigned apicid_8131_2; + +extern unsigned sbdn3; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int i, bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping*/ + + dword = 0x0120d218; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x12008a00; + pci_write_config32(dev, 0x80, dword); + + dword = 0x0000007d; + pci_write_config32(dev, 0x84, dword); + + } + + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + } + + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1); + +// Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 + +// Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 + +// Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 + +// Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 + +// Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 + +//Slot PCIE x16 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); + } + +//Slot PCIE x4 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); + } + +//Onboard ati + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 + +//Channel B of 8131 + + +//Onboard Broadcom NIC + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 + } + +//Channel A of 8131 + +//Slot 4 PCIX 133/100/66 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 + } + +//Slot 3 PCIX 133/100/66 SoDIMM PCI + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 + } + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/winent/mb6047/resourcemap.c b/src/mainboard/winent/mb6047/resourcemap.c new file mode 100644 index 0000000..d76f1d6 --- /dev/null +++ b/src/mainboard/winent/mb6047/resourcemap.c @@ -0,0 +1,266 @@ +/* + * Tyan S2891 needs a different resource map + * + */ + +static void setup_s2891_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} + diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c new file mode 100644 index 0000000..9cd3a4a --- /dev/null +++ b/src/mainboard/winent/mb6047/romstage.c @@ -0,0 +1,148 @@ +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/nvidia/ck804/early_smbus.h" +#include "northbridge/amd/amdk8/raminit.h" +#include "lib/delay.c" +#include "cpu/x86/lapic.h" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627hf/early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void memreset_setup(void) { } +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + uint32_t dword; + uint8_t byte; + + /* subject decoding*/ + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1<<0) | (1<<1); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + +#if 1 + /* s2891 has onboard LPC port 80 */ + /*Hope I can enable port 80 here + It will decode port 80 to LPC, If you are using PCI post code you can not do this */ + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); +#endif +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, +#endif + }; + + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8]; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + sio_setup(); + } + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx); + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_s2891_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + needs_reset |= ht_setup_chains_x(); + needs_reset |= ck804_early_setup_x(); + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); +#endif + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + print_pci_devices(); + dump_pci_devices(); +#endif + + post_cache_as_ram(); +}

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coreboot-gerrit October 2013