New patch to review for coreboot: 2ea776a dmp/vortex86ex: Initialize I2C controller base address/IRQ

[Andrew Wu]

Andrew Wu ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976

-gerrit

commit 2ea776ae7029f7aeedc8a5edcc4ce269ae2f00c0
Author: Andrew Wu 
Date:   Wed Oct 16 13:08:30 2013 +0800

dmp/vortex86ex: Initialize I2C controller base address/IRQ

Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
    Signed-off-by: Andrew Wu 
---
 src/southbridge/dmp/vortex86ex/southbridge.c | 15 +++++++++++++++
 src/southbridge/dmp/vortex86ex/southbridge.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index d8914c0..99a5a69 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = {
 #define PIDE_IRQ 5

#define SPI1_IRQ 10
+#define I2C0_IRQ 10
 #define MOTOR_IRQ 11

/* RT0-3 IRQs. */
@@ -89,6 +90,9 @@ static const unsigned char irq_to_int_routing[16] = {
 #define LPT_PDMAS 0
 #define LPT_DREQS 0

+/* internal I2C */
+#define I2C_BASE 0xfb00
+
 /* Post codes */
 #define POST_KBD_FW_UPLOAD 0x06
 #define POST_KBD_CHK_READY 0x07
@@ -418,6 +422,16 @@ static void ex_sb_uart_init(struct device *dev)
    //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
 }

+static void i2c_init(struct device *dev)
+{
+	u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];
+	u32 cfg = 0;
+	cfg |= 1 << 31;			// UE = enabled.
+	cfg |= (mapped_irq << 16);	// IIRT0.
+	cfg |= I2C_BASE;		// UIOA.
+	pci_write_config32(dev, SB_REG_II2CCR, cfg);
+}
+
 static int get_rtc_update_in_progress(void)
 {
    if (cmos_read(RTC_REG_A) & RTC_UIP)
@@ -566,6 +580,7 @@ static void southbridge_init(struct device *dev)
    if (dev->device == 0x6011) {
    	ex_sb_gpio_init(dev);
    	ex_sb_uart_init(dev);
+		i2c_init(dev);
    }
    pci_routing_fixup(dev);

diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h
index 0cc28fa..316d30a 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.h
+++ b/src/southbridge/dmp/vortex86ex/southbridge.h
@@ -36,6 +36,7 @@
 #define	SB_REG_IPFCR		0xc0
 #define	SB_REG_FRWPR		0xc4
 #define	SB_REG_STRAP		0xce
+#define	SB_REG_II2CCR		0xd4

#define	SB1			PCI_DEV(0, 7, 1)
 #define	SB1_REG_EXT_PIRQ_ROUTE2	0xb4