coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: b1581cd CBMEM: Fail builds on missing get_top_of_ram()
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3969 -gerrit commit b1581cd573ed4efb840e80557e4cfd5c7f3d3c43 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 12 00:22:57 2013 +0300 CBMEM: Fail builds on missing get_top_of_ram() Dummy get_top_of_ram() is removed from romstage to fail already at build-time for cases where cbmem_initialize() would not complete. The mechanisms behind CAR_GLOBAL migration only work correctly when romstage can succesfully make the cbmem_initialize() call. Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 58ccbca..6a12263 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -18,12 +18,6 @@ #include <console/console.h> #include <cbmem.h> -unsigned long __attribute__((weak)) get_top_of_ram(void) -{ - printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); - return 0; -} - #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { @@ -37,9 +31,8 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) *size = 0; } } -#endif -#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) { /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ @@ -54,4 +47,12 @@ void set_top_of_ram(uint64_t ramtop) backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } + +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} +#endif /* !__PRE_RAM__ */ + #endif

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Patch set updated for coreboot: 06a98e0 Have option of timestamps, CBMEM console and usbdebug for most boards
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3970 -gerrit commit 06a98e0b48bac75474ddef00574dc19d16e1f650 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 11 21:14:59 2013 +0300 Have option of timestamps, CBMEM console and usbdebug for most boards As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage, and have no CAR migration, these features are available for ramstage only. Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/lib/romstage_console.c | 6 +++--- src/console/Kconfig | 1 - src/console/console.c | 4 ++-- src/include/timestamp.h | 2 +- src/lib/usbdebug.c | 6 ++---- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4af8002..10f8c18 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -190,7 +190,7 @@ config DYNAMIC_CBMEM config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) + default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 1c3141c..fc90085 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -49,13 +49,13 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) usbdebug_tx_byte(dbgp_console_output(), byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_tx_byte(byte); #endif #if CONFIG_SPKMODEM @@ -74,7 +74,7 @@ void console_tx_flush(void) #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) usbdebug_tx_flush(dbgp_console_output()); #endif } diff --git a/src/console/Kconfig b/src/console/Kconfig index 9bfb6e9..f415d93 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -274,7 +274,6 @@ config CONSOLE_NE2K_IO_PORT boundary, qemu needs broader align) config CONSOLE_CBMEM - depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) bool "Send console output to a CBMEM buffer" default n help diff --git a/src/console/console.c b/src/console/console.c index 06a4604..014a4f7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -113,13 +113,13 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_CBMEM && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) cbmemc_init(); #endif #if CONFIG_SPKMODEM spkmodem_init(); #endif -#if CONFIG_USBDEBUG && !defined(__BOOT_BLOCK__) +#if CONFIG_USBDEBUG && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) usbdebug_init(); #endif diff --git a/src/include/timestamp.h b/src/include/timestamp.h index edc0076..9e780c3 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -54,7 +54,7 @@ enum timestamp_id { TS_SELFBOOT_JUMP = 99, }; -#if CONFIG_COLLECT_TIMESTAMPS +#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) #include <cpu/x86/tsc.h> void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 3faec10..e5f7902 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -579,13 +579,13 @@ err: } #endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */ -#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE static void enable_usbdebug(void) { +#if defined(__PRE_RAM__) || !(CONFIG_EARLY_CONSOLE && CONFIG_EARLY_CBMEM_INIT) pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); -} #endif +} static void set_debug_port(unsigned int port) { @@ -1038,8 +1038,6 @@ int usbdebug_init(void) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif -#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE enable_usbdebug(); -#endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); }

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Patch set updated for coreboot: ec39a87 Revert "CBMEM: Always have early initialisation"
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3968 -gerrit commit ec39a876e0dafef0b3cfe83b3b0df908ecfc034e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 11 22:08:02 2013 +0300 Revert "CBMEM: Always have early initialisation" This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34. While things appeared to work, there were actually invalid references to CAR storage after CAR was torn down on boards without EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be restricted to boards that handle CAR migration properly. Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 12 +++++++++++- src/arch/x86/boot/Makefile.inc | 3 ++- src/console/Kconfig | 1 + src/cpu/x86/Makefile.inc | 3 ++- src/lib/Makefile.inc | 5 +++-- src/lib/cbmem.c | 4 ++++ src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 4 ++++ src/mainboard/intel/emeraldlake2/Kconfig | 1 + src/mainboard/kontron/ktqm77/Kconfig | 1 + src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/via/epia-m850/romstage.c | 2 ++ src/northbridge/intel/sandybridge/raminit.c | 2 ++ 20 files changed, 42 insertions(+), 5 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 1c35fb3..4af8002 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -170,9 +170,19 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 +config EARLY_CBMEM_INIT + bool + default n + help + Make coreboot initialize the CBMEM structures while running in ROM + stage. This is useful when the ROM stage wants to communicate + some, for instance, execution timestamps. It needs support in + romstage.c and should be enabled by the board's Kconfig. + config DYNAMIC_CBMEM bool "The CBMEM space is dynamically grown." default n + select EARLY_CBMEM_INIT help Instead of reserving a static amount of CBMEM space the CBMEM area grows dynamically. CBMEM can be used both in romstage (after @@ -180,7 +190,7 @@ config DYNAMIC_CBMEM config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n + depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d3a5f21..4b4a841 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,4 +1,5 @@ -romstage-y += cbmem.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c diff --git a/src/console/Kconfig b/src/console/Kconfig index f415d93..9bfb6e9 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -274,6 +274,7 @@ config CONSOLE_NE2K_IO_PORT boundary, qemu needs broader align) config CONSOLE_CBMEM + depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) bool "Send console output to a CBMEM buffer" default n help diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 311dcc1..ca755de 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1 +1,2 @@ -romstage-$(CONFIG_CACHE_AS_RAM) += car.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += car.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1455e4c..6110b88 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -50,7 +50,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c -ifeq ($(CONFIG_CACHE_AS_RAM),y) +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -108,7 +108,8 @@ ramstage-y += dynamic_cbmem.c romstage-y += dynamic_cbmem.c else ramstage-y += cbmem.c -romstage-$(CONFIG_CACHE_AS_RAM) += cbmem.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c endif # CONFIG_DYNAMIC_CBMEM ramstage-y += cbmem_info.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 8a39647..de49816 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -95,6 +95,7 @@ void cbmem_late_set_table(uint64_t base, uint64_t size) * - suspend/resume backup memory */ +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) static void cbmem_init(void) { uint64_t baseaddr, size; @@ -119,6 +120,7 @@ static void cbmem_init(void) .size = size - CBMEM_TOC_RESERVED }; } +#endif int cbmem_reinit(void) { @@ -218,6 +220,7 @@ void *cbmem_find(u32 id) return (void *)NULL; } +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { @@ -241,6 +244,7 @@ int cbmem_initialize(void) return rv; } +#endif #ifndef __PRE_RAM__ static void init_cbmem_post_device(void *unused) diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 2eed55b..b462b8c 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_256 + select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 43bba46..9d78bb8 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES # select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_256 + select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index d35be8d..e9ad6ef 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS + select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index d040599..b74c604 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHROMEOS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT + select EARLY_CBMEM_INIT select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 1108b13..191e856 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS + select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index a0700af..8a961ea 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -296,7 +296,11 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; +#if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); +#else + cbmem_was_initted = cbmem_reinit(); +#endif #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 1ad50d9..fd98485 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select GFXUMA #select CHROMEOS + select EARLY_CBMEM_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index d379f6f..e9d1ce7 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select GFXUMA + select EARLY_CBMEM_INIT select ENABLE_VMX select HAVE_MRC diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index ec03534..0f0670e 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select EARLY_CBMEM_INIT config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 8eb159b..72aeef8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select EARLY_CBMEM_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 13c8748..91dc3b6 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 select DRIVERS_GENERIC_IOAPIC + select EARLY_CBMEM_INIT select HAVE_MRC config MAINBOARD_DIR diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 17f854f..f4f8e4d 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F + select EARLY_CBMEM_INIT select HAVE_MRC config MAINBOARD_DIR diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 473e60e..39f4253 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -94,7 +94,9 @@ void main(unsigned long bist) print_debug("We passed RAM verify\n"); /* We got RAM working, now we can write the timestamps to RAM */ +#if CONFIG_EARLY_CBMEM_INIT cbmem_initialize(); +#endif timestamp_add_now(TS_END_ROMSTAGE); /* FIXME: See if this is needed or take this out please */ /* Disable Memcard and SDIO */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index db96202..3b321d7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -58,6 +58,7 @@ static void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; +#if CONFIG_EARLY_CBMEM_INIT struct mrc_data_container *mrcdata; int output_len = ALIGN(pei_data->mrc_output_len, 16); @@ -83,6 +84,7 @@ static void save_mrc_data(struct pei_data *pei_data) mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, mrcdata->mrc_data_size); +#endif /* Save the MRC seed values to CMOS */ cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);

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Patch set updated for coreboot: c764387 CBMEM: Fail builds on missing get_top_of_ram()
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3969 -gerrit commit c764387883078d53a69197f95bd4d29da393752e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 12 00:22:57 2013 +0300 CBMEM: Fail builds on missing get_top_of_ram() Dummy get_top_of_ram() is removed from romstage to fail already at build-time for cases where cbmem_initialize() would not complete. The mechanisms behind CAR_GLOBAL migration only work correctly when romstage can succesfully make the cbmem_initialize() call. Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 58ccbca..6a12263 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -18,12 +18,6 @@ #include <console/console.h> #include <cbmem.h> -unsigned long __attribute__((weak)) get_top_of_ram(void) -{ - printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); - return 0; -} - #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { @@ -37,9 +31,8 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) *size = 0; } } -#endif -#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) { /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ @@ -54,4 +47,12 @@ void set_top_of_ram(uint64_t ramtop) backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } + +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} +#endif /* !__PRE_RAM__ */ + #endif

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Patch set updated for coreboot: 93debb1 Have option of timestamps, CBMEM console and usbdebug for most boards
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3970 -gerrit commit 93debb1f9344cb13802393da7aaed9535bf885ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 11 21:14:59 2013 +0300 Have option of timestamps, CBMEM console and usbdebug for most boards As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage, and have no CAR migration, these features are available for ramstage only. Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/lib/romstage_console.c | 6 +++--- src/console/Kconfig | 1 - src/console/console.c | 4 ++-- src/include/timestamp.h | 2 +- src/lib/usbdebug.c | 6 ++---- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4af8002..10f8c18 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -190,7 +190,7 @@ config DYNAMIC_CBMEM config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) + default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 1c3141c..fc90085 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -49,13 +49,13 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) usbdebug_tx_byte(dbgp_console_output(), byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_tx_byte(byte); #endif #if CONFIG_SPKMODEM @@ -74,7 +74,7 @@ void console_tx_flush(void) #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) usbdebug_tx_flush(dbgp_console_output()); #endif } diff --git a/src/console/Kconfig b/src/console/Kconfig index 9bfb6e9..f415d93 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -274,7 +274,6 @@ config CONSOLE_NE2K_IO_PORT boundary, qemu needs broader align) config CONSOLE_CBMEM - depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM) bool "Send console output to a CBMEM buffer" default n help diff --git a/src/console/console.c b/src/console/console.c index 06a4604..014a4f7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -113,13 +113,13 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_CBMEM && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) cbmemc_init(); #endif #if CONFIG_SPKMODEM spkmodem_init(); #endif -#if CONFIG_USBDEBUG && !defined(__BOOT_BLOCK__) +#if CONFIG_USBDEBUG && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) usbdebug_init(); #endif diff --git a/src/include/timestamp.h b/src/include/timestamp.h index edc0076..9e780c3 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -54,7 +54,7 @@ enum timestamp_id { TS_SELFBOOT_JUMP = 99, }; -#if CONFIG_COLLECT_TIMESTAMPS +#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) #include <cpu/x86/tsc.h> void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 3faec10..e5f7902 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -579,13 +579,13 @@ err: } #endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */ -#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE static void enable_usbdebug(void) { +#if defined(__PRE_RAM__) || !(CONFIG_EARLY_CONSOLE && CONFIG_EARLY_CBMEM_INIT) pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); -} #endif +} static void set_debug_port(unsigned int port) { @@ -1038,8 +1038,6 @@ int usbdebug_init(void) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif -#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE enable_usbdebug(); -#endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); }

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Patch merged into coreboot/master: 3fa1a13 dmp/vortex86ex: Initialize PS/2 keyboard.
by gerrit＠coreboot.org 13 Oct '13

13 Oct '13

the following patch was just integrated into master: commit 3fa1a13f62fe805a4592eaa551cd9d5713613f91 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 9 18:57:20 2013 +0800 dmp/vortex86ex: Initialize PS/2 keyboard. Call pc_keyboard_init function in southbridge. It makes PS/2 keyboard work in coreinfo payload. Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3957 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3957 for details. -gerrit

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Patch merged into coreboot/master: 7a00ca7 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
by gerrit＠coreboot.org 13 Oct '13

13 Oct '13

the following patch was just integrated into master: commit 7a00ca75d70ceb336e189851dca06b363139ed96 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Oct 12 21:29:26 2013 +0200 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()` Change-Id: I7fc7819c329c058472031e82237be5c170b277f4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3965 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/3965 for details. -gerrit

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Patch set updated for coreboot: f833ff7 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
by Jonathan A. Kollasch 13 Oct '13

13 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3963 -gerrit commit f833ff7b2ddaf6dbbd046709a38eaaa3aca2772b Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 16:14:18 2013 -0500 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1 Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000 (that is, outside the range of bus 0 address space). This causes IOAPIC interrupts to fail to work under Linux. This issue was originally unnoticed by me when testing as sanity checking such as this is not done by NetBSD. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 4b33a3c..b3a9b00 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -53,15 +53,10 @@ static void lpc_common_init(device_t dev) { - u8 byte; u32 dword; struct resource *res; /* I/O APIC initialization. */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable APIC. */ - pci_write_config8(dev, 0x74, byte); - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ @@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev) static void ck804_lpc_set_resources(device_t dev) { + u8 byte; struct resource *res; pci_dev_set_resources(dev); @@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev) /* APIC */ res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { + byte = pci_read_config8(dev, 0x74); + byte |= (1 << 1); /* enable access to PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); + byte |= (1 << 0); /* enable decode of IOAPIC space */ + byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); } /* HPET */

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Patch set updated for coreboot: d487a26 ck804: obtain I/O APIC base address for ACPI MADT from allocator
by Jonathan A. Kollasch 13 Oct '13

13 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3960 -gerrit commit d487a267423c0df8af26839a65e213e77735bba3 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 14:58:39 2013 -0500 ck804: obtain I/O APIC base address for ACPI MADT from allocator Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/acpi_tables.c | 25 +++++++++++---------- src/mainboard/tyan/s2891/acpi_tables.c | 21 +++++++++-------- src/mainboard/tyan/s2892/acpi_tables.c | 21 +++++++++-------- src/mainboard/tyan/s2895/acpi_tables.c | 41 +++++++++++++++++++--------------- 4 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index da4ef8d..ee8e81f 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -48,28 +48,29 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { - unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) #error untested config - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* IRQ of timer */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 890e239..42d9152 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 890e239..42d9152 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index b7cb475..1974171 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x00080d7d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x00080d7d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); @@ -67,17 +70,19 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write second NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, - apic_addr, 0x20); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, + res->base, 0x20); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? - pci_write_config32(dev, 0x80, 0x00000000); - pci_write_config32(dev, 0x84, 0x00000d00); // Same here. + pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? + pci_write_config32(dev, 0x80, 0x00000000); + pci_write_config32(dev, 0x84, 0x00000d00); // Same here. #endif - } /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

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Patch set updated for coreboot: df95666 ck804: obtain stored IOAPIC address from allocator instead of register
by Jonathan A. Kollasch 13 Oct '13

13 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3961 -gerrit commit df95666d42556eeb4f58d70904fee1a7b75704b9 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 15:52:30 2013 -0500 ck804: obtain stored IOAPIC address from allocator instead of register Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d132803..4b33a3c 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -32,6 +32,7 @@ #include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <stdlib.h> +#include <assert.h> #include "ck804.h" #define CK804_CHIP_REV 2 @@ -54,14 +55,16 @@ static void lpc_common_init(device_t dev) { u8 byte; u32 dword; + struct resource *res; /* I/O APIC initialization. */ byte = pci_read_config8(dev, 0x74); byte |= (1 << 0); /* Enable APIC. */ pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ - setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */ + res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ + ASSERT(res != NULL); + setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ #if 1 dword = pci_read_config32(dev, 0xe4);

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coreboot-gerrit October 2013