coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

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159 discussions

Patch set updated for coreboot: c018dab northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
by Patrick Georgi 13 Oct '13

13 Oct '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3965 -gerrit commit c018dabd9ea561894cc6c379a23e8dfd818aa34f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Oct 12 21:29:26 2013 +0200 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()` Trying to build the ASUS M2V-MX SE, gcc aborts with the following error. $ ./util/crossgcc/xgcc/i386-elf/bin/gcc --version gcc (coreboot toolchain v1.20 December 4th, 2012) 4.7.3 $ make V=1 [...] CC romstage.inc In file included from src/northbridge/amd/amdk8/raminit_f.c:2905:0, from src/mainboard/asus/m2v-mx_se/romstage.c:67: src/northbridge/amd/amdk8/raminit_f_dqs.c: In function 'setup_mtrr_dqs': src/northbridge/amd/amdk8/raminit_f_dqs.c:1738:11: error: variable 'reg' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors make: *** [build/mainboard/asus/m2v-mx_se/romstage.pre.inc] Error 1 Removing the variable `reg` solves this issue. Change-Id: I7fc7819c329c058472031e82237be5c170b277f4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 08a3bab..4438340 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1735,7 +1735,6 @@ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { - unsigned reg; msr_t msr; #if 0 @@ -1752,7 +1751,7 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); + range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); //[4G, TOM2) if(tom2_k) {

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New patch to review for coreboot: c959eff northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
by Paul Menzel 12 Oct '13

12 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3965 -gerrit commit c959eff45df65516731c1d5a0cbf137ce1d13546 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Oct 12 21:29:26 2013 +0200 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()` Trying to build the ASUS M2V-MX SE, gcc aborts with the following error. $ ./util/crossgcc/xgcc/i386-elf/bin/gcc --version gcc (coreboot toolchain v1.20 December 4th, 2012) 4.7.3 $ make V=1 […] CC romstage.inc /src/coreboot/util/crossgcc/xgcc/bin/i386-elf-gcc -MMD -Isrc -Isrc/include -Ibuild -Isrc/arch/x86/include -Isrc/device/oprom/include -include src/include/kconfig.h -Os -pipe -g -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wstrict-aliasing -Wshadow -Werror -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -D__PRE_RAM__ -Isrc -I. -Ibuild -c -S src/mainboard/asus/m2v-mx_se/romstage.c -o build/mainboard/asus/m2v-mx_se/romstage.pre.inc In file included from src/northbridge/amd/amdk8/raminit_f.c:2905:0, from src/mainboard/asus/m2v-mx_se/romstage.c:67: src/northbridge/amd/amdk8/raminit_f_dqs.c: In function 'setup_mtrr_dqs': src/northbridge/amd/amdk8/raminit_f_dqs.c:1738:11: error: variable 'reg' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors make: *** [build/mainboard/asus/m2v-mx_se/romstage.pre.inc] Error 1 Removing the variable `reg` solves this issue. (The question is, why haven’t our build tests done by Jenkins caught this.) Change-Id: I7fc7819c329c058472031e82237be5c170b277f4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 08a3bab..4438340 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1735,7 +1735,6 @@ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { - unsigned reg; msr_t msr; #if 0 @@ -1752,7 +1751,7 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); + range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); //[4G, TOM2) if(tom2_k) {

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New patch to review for coreboot: 8f9135b Kratos-X1: Initial support for Micro Passion Kratos-X1
by David Robinson 12 Oct '13

12 Oct '13

David Robinson (info(a)micropassion.co.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3964 -gerrit commit 8f9135bcf4d07bc3581f91521a45a4c3f54a19cd Author: David Robinson <info(a)micropassion.co.uk> Date: Sat Oct 12 19:14:33 2013 +0100 Kratos-X1: Initial support for Micro Passion Kratos-X1 Initial support for Micro Passion Kratos-X1 PICO ITX single board computer featuring an AMD G-Series SOC (FT3). The configuration includes an example of soldered down DDR3 (No SPD). Removed non standard line endings. Change-Id: I966b891a2fa562c5c29201cb7e7237b4ddfd107a Signed-off-by: David Robinson <info(a)micropassion.co.uk> --- src/mainboard/micropassion/Kconfig | 32 +- src/mainboard/micropassion/kratosx1/BiosCallOuts.c | 4 +- src/mainboard/micropassion/kratosx1/acpi/ide.asl | 250 -------------- src/mainboard/micropassion/kratosx1/acpi/sata.asl | 130 -------- src/mainboard/micropassion/kratosx1/devicetree.cb | 2 +- src/mainboard/micropassion/kratosx1/dsdt.asl | 2 +- src/mainboard/micropassion/kratosx1/get_bus_conf.c | 368 ++++++++++----------- src/mainboard/micropassion/kratosx1/romstage.c | 2 +- 8 files changed, 205 insertions(+), 585 deletions(-) diff --git a/src/mainboard/micropassion/Kconfig b/src/mainboard/micropassion/Kconfig index 7045161..7dec41b 100755 --- a/src/mainboard/micropassion/Kconfig +++ b/src/mainboard/micropassion/Kconfig @@ -1,16 +1,16 @@ -if VENDOR_MICROPASSION - -choice - prompt "Mainboard model" - -config BOARD_MICROPASSION_KRATOSX1 - bool "KRATOS-X1" -endchoice - -source "src/mainboard/micropassion/kratosx1/Kconfig" - -config MAINBOARD_VENDOR - string - default "Micro Passion Ltd" - -endif # VENDOR_MICROPASSION +if VENDOR_MICROPASSION + +choice + prompt "Mainboard model" + +config BOARD_MICROPASSION_KRATOSX1 + bool "KRATOS-X1" +endchoice + +source "src/mainboard/micropassion/kratosx1/Kconfig" + +config MAINBOARD_VENDOR + string + default "Micro Passion Ltd" + +endif # VENDOR_MICROPASSION diff --git a/src/mainboard/micropassion/kratosx1/BiosCallOuts.c b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c index 6b62e0d..fb955a8 100755 --- a/src/mainboard/micropassion/kratosx1/BiosCallOuts.c +++ b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd + * Copyright (C) 2013 Micro Passion Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,7 +120,7 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_READ_SPD_PARAMS * Params = (AGESA_READ_SPD_PARAMS *) ConfigPtr; printk(BIOS_DEBUG, "BiosReadSpd: %d %d %d\n", Params->SocketId, Params->MemChannelId, Params->DimmId); - + memcpy(Params->Buffer, SPD_2GB_1R8_1333, 256); Status = AGESA_SUCCESS; diff --git a/src/mainboard/micropassion/kratosx1/acpi/ide.asl b/src/mainboard/micropassion/kratosx1/acpi/ide.asl deleted file mode 100755 index 853dc13..0000000 --- a/src/mainboard/micropassion/kratosx1/acpi/ide.asl +++ /dev/null @@ -1,250 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/micropassion/kratosx1/acpi/sata.asl b/src/mainboard/micropassion/kratosx1/acpi/sata.asl index 3d19222..5e4d1fe 100755 --- a/src/mainboard/micropassion/kratosx1/acpi/sata.asl +++ b/src/mainboard/micropassion/kratosx1/acpi/sata.asl @@ -18,133 +18,3 @@ */ /* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/micropassion/kratosx1/devicetree.cb b/src/mainboard/micropassion/kratosx1/devicetree.cb index 451d290..28bc1a5 100755 --- a/src/mainboard/micropassion/kratosx1/devicetree.cb +++ b/src/mainboard/micropassion/kratosx1/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/micropassion/kratosx1/dsdt.asl b/src/mainboard/micropassion/kratosx1/dsdt.asl index 78d9bca..ee5e7ac 100755 --- a/src/mainboard/micropassion/kratosx1/dsdt.asl +++ b/src/mainboard/micropassion/kratosx1/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "MPL ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/micropassion/kratosx1/get_bus_conf.c b/src/mainboard/micropassion/kratosx1/get_bus_conf.c index 5413986..2147089 100755 --- a/src/mainboard/micropassion/kratosx1/get_bus_conf.c +++ b/src/mainboard/micropassion/kratosx1/get_bus_conf.c @@ -1,184 +1,184 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <string.h> -#include <stdint.h> -#include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" - -#define ACPI_MMIO_BASE 0xFED80000 - -/* Global variables for MB layouts and these will be shared by irqtable mptable - * and acpi_tables busnum is default. - */ -u8 bus_isa; -u8 bus_yangtze[3]; -u32 apicid_yangtze; - -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 bus_type[256]; -u32 sbdn_yangtze; - -static u32 get_bus_conf_done = 0; - -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif -void get_bus_conf(void) -{ - u32 apicid_base; - u32 status; - device_t pcidev; - u16 temp; - u32 * Ptr32; - u32 value; - - device_t dev; - int i, j; - - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); - - sbdn_yangtze = 0; - - for (i = 0; i < 3; i++) { - bus_yangtze[i] = 0; - } - - for (i = 0; i < 256; i++) { - bus_type[i] = 0; /* default ISA bus. */ - } - - bus_type[0] = 1; /* pci */ - - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; - - /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); - - if (dev) { - bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_yangtze[1]; j < bus_isa; j++) - bus_type[j] = 1; - } - - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); - if (dev) { - bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } - } - for (j = bus_yangtze[2]; j < bus_isa; j++) - bus_type[j] = 1; - - /* I/O APICs: APIC ID Version State Address */ - bus_isa = 10; - apicid_base = CONFIG_MAX_CPUS; - apicid_yangtze = apicid_base; - - - //Setup Ethernet LED Configuration - pcidev = dev_find_device(0x10EC, 0x8168, 0); - if (pcidev) - { - temp = pci_read_config16(pcidev, 0x10); - temp &= 0xFFFE; - printk(BIOS_DEBUG, "Found Realtek Ethernet controller with IO address: %x\n", temp); - outw (0xFF, (temp + 0x18)); - } - - Ptr32 = (u32 *) (ACPI_MMIO_BASE + 0xE00 + 0x00); //GPPClkCntrl - *Ptr32 &= ~0x0000; - *Ptr32 |= 0x430F; //Setup PCIe clocks based on clk_req lines - - //Setup PSI_L VID threshold - pcidev = dev_find_slot(0, PCI_DEVFN(0x18, 3)); - if (pcidev) - { - temp = pci_read_config16(pcidev, 0xA0); - temp &= 0xFF00; - temp |= 0xE2; - pci_write_config16(pcidev, 0xA0, temp); - } - -} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Micro Passion Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" + +#define ACPI_MMIO_BASE 0xFED80000 + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_yangtze[3]; +u32 apicid_yangtze; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_yangtze; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + device_t pcidev; + u16 temp; + u32 * Ptr32; + u32 value; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + + sbdn_yangtze = 0; + + for (i = 0; i < 3; i++) { + bus_yangtze[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; + + /* yangtze */ + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + + if (dev) { + bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_yangtze[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + if (dev) { + bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_yangtze[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_yangtze = apicid_base; + + + //Setup Ethernet LED Configuration + pcidev = dev_find_device(0x10EC, 0x8168, 0); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0x10); + temp &= 0xFFFE; + printk(BIOS_DEBUG, "Found Realtek Ethernet controller with IO address: %x\n", temp); + outw (0xFF, (temp + 0x18)); + } + + Ptr32 = (u32 *) (ACPI_MMIO_BASE + 0xE00 + 0x00); //GPPClkCntrl + *Ptr32 &= ~0x0000; + *Ptr32 |= 0x430F; //Setup PCIe clocks based on clk_req lines + + //Setup PSI_L VID threshold + pcidev = dev_find_slot(0, PCI_DEVFN(0x18, 3)); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0xA0); + temp &= 0xFF00; + temp |= 0xE2; + pci_write_config16(pcidev, 0xA0, temp); + } + +} diff --git a/src/mainboard/micropassion/kratosx1/romstage.c b/src/mainboard/micropassion/kratosx1/romstage.c index 51b6e86..7314223 100755 --- a/src/mainboard/micropassion/kratosx1/romstage.c +++ b/src/mainboard/micropassion/kratosx1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd + * Copyright (C) 2013 Micro Passion Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by

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Patch set updated for coreboot: 85816e6 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
by Jonathan A. Kollasch 12 Oct '13

12 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3896 -gerrit commit 85816e64e0c50630ba4cc6ed582975db2add1afa Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 1 + src/arch/x86/Makefile.inc | 1 + util/xcompile/xcompile | 1 + 3 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..b709d14 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ARCH-$(CONFIG_ARCH_X86) := i386 ifneq ($(INNER_SCANBUILD),y) CC := $(CC_$(ARCH-y)) endif +CPP := $(CPP_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) NM := $(NM_$(ARCH-y)) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b3b82b9..dee56c5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -427,6 +427,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index de6084d..5388889 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -117,6 +117,7 @@ report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm

1 0

Patch set updated for coreboot: 3974220 ck804: obtain I/O APIC base address for ACPI MADT from allocator
by Jonathan A. Kollasch 12 Oct '13

12 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3960 -gerrit commit 3974220102322536027e2b053c4bea56113da39d Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 14:58:39 2013 -0500 ck804: obtain I/O APIC base address for ACPI MADT from allocator Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/acpi_tables.c | 25 +++++++++++---------- src/mainboard/tyan/s2891/acpi_tables.c | 21 +++++++++-------- src/mainboard/tyan/s2892/acpi_tables.c | 21 +++++++++-------- src/mainboard/tyan/s2895/acpi_tables.c | 41 +++++++++++++++++++--------------- 4 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index da4ef8d..ee8e81f 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -48,28 +48,29 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { - unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) #error untested config - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* IRQ of timer */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 890e239..42d9152 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 890e239..42d9152 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x0000007d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index b7cb475..1974171 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -32,23 +32,26 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; + struct resource *res; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - apic_addr, 0); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + res->base, 0); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0120d218); - pci_write_config32(dev, 0x80, 0x12008a00); - pci_write_config32(dev, 0x84, 0x00080d7d); + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x00080d7d); #endif - } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); @@ -67,17 +70,19 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write second NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, - apic_addr, 0x20); - /* Initialize interrupt mapping if mptable.c didn't. */ + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, + res->base, 0x20); + /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) - pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? - pci_write_config32(dev, 0x80, 0x00000000); - pci_write_config32(dev, 0x84, 0x00000d00); // Same here. + pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? + pci_write_config32(dev, 0x80, 0x00000000); + pci_write_config32(dev, 0x84, 0x00000d00); // Same here. #endif - } /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

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Patch merged into coreboot/master: 8ad6e78 Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization
by gerrit＠coreboot.org 12 Oct '13

12 Oct '13

the following patch was just integrated into master: commit 8ad6e78778b036cf2c9bc455376a8599e0bcb759 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 13:50:04 2013 -0500 Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/3959 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/3959 for details. -gerrit

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Patch set updated for coreboot: e876697 Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization
by Paul Menzel 12 Oct '13

12 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3959 -gerrit commit e876697109fb4916cc8e6f761936cafd3ef266f5 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 13:50:04 2013 -0500 Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/acpi_tables.c | 14 +++---------- src/mainboard/tyan/s2891/acpi_tables.c | 18 +++++------------ src/mainboard/tyan/s2892/acpi_tables.c | 18 +++++------------ src/mainboard/tyan/s2895/acpi_tables.c | 36 ++++++++++------------------------ 4 files changed, 23 insertions(+), 63 deletions(-) diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index 6bd3183a..da4ef8d 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -65,17 +65,9 @@ unsigned long acpi_fill_madt(unsigned long current) /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) #error untested config - { - u32 dword; - dword = 0x0120d218; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); - } + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); #endif } diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index d3cb214..890e239 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -43,19 +43,11 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, apic_addr, 0); /* Initialize interrupt mapping if mptable.c didn't. */ - #if (!CONFIG_GENERATE_MP_TABLE) - { - u32 dword; - dword = 0x0120d218; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); - } - #endif +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); +#endif } /* Write AMD 8131 two IOAPICs. */ diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index d3cb214..890e239 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -43,19 +43,11 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, apic_addr, 0); /* Initialize interrupt mapping if mptable.c didn't. */ - #if (!CONFIG_GENERATE_MP_TABLE) - { - u32 dword; - dword = 0x0120d218; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); - } - #endif +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x0000007d); +#endif } /* Write AMD 8131 two IOAPICs. */ diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index 8f69c70..b7cb475 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -43,19 +43,11 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, apic_addr, 0); /* Initialize interrupt mapping if mptable.c didn't. */ - #if (!CONFIG_GENERATE_MP_TABLE) - { - u32 dword; - dword = 0x0120d218; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0x00080d7d; - pci_write_config32(dev, 0x84, dword); - } - #endif +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0120d218); + pci_write_config32(dev, 0x80, 0x12008a00); + pci_write_config32(dev, 0x84, 0x00080d7d); +#endif } /* Write AMD 8131 two IOAPICs. */ @@ -80,19 +72,11 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, apic_addr, 0x20); /* Initialize interrupt mapping if mptable.c didn't. */ - #if (!CONFIG_GENERATE_MP_TABLE) - { - u32 dword; - dword = 0x0000d218; // Why does the factory BIOS have 0? - pci_write_config32(dev, 0x7c, dword); - - dword = 0x00000000; - pci_write_config32(dev, 0x80, dword); - - dword = 0x00000d00; // Same here. - pci_write_config32(dev, 0x84, dword); - } - #endif +#if (!CONFIG_GENERATE_MP_TABLE) + pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? + pci_write_config32(dev, 0x80, 0x00000000); + pci_write_config32(dev, 0x84, 0x00000d00); // Same here. +#endif } /* IRQ9 */

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New patch to review for coreboot: 07e8b26 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
by Jonathan A. Kollasch 11 Oct '13

11 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3963 -gerrit commit 07e8b2656b943f9c56825c4ad77f1a832f3c90fb Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 16:14:18 2013 -0500 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1 Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000. This causes IOAPIC interrupts to fail to work under Linux. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 4b33a3c..d52d1e7 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -53,15 +53,10 @@ static void lpc_common_init(device_t dev) { - u8 byte; u32 dword; struct resource *res; /* I/O APIC initialization. */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable APIC. */ - pci_write_config8(dev, 0x74, byte); - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ @@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev) static void ck804_lpc_set_resources(device_t dev) { + u8 byte; struct resource *res; pci_dev_set_resources(dev); @@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev) /* APIC */ res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { + byte = pci_read_config8(dev, 0x74); + byte |= (1 << 1); /* enables access to PCI_BASE_ADDRESS_1 */ + byte |= (1 << 0); /* enables decode of IOAPIC space */ + pci_write_config8(dev, 0x74, byte); pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); + byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); } /* HPET */

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Patch set updated for coreboot: d998ccd ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14
by Jonathan A. Kollasch 11 Oct '13

11 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3962 -gerrit commit d998ccdcfcda8d9f755e207695105f81c82a725b Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 16:09:37 2013 -0500 ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14 Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c3f24bc..4b33a3c 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -205,7 +205,7 @@ static void ck804_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) { - res = find_resource(dev, 0x14); /* IOAPIC */ + res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ if (res) { res->base = IO_APIC_ADDR; res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; @@ -226,9 +226,9 @@ static void ck804_lpc_set_resources(device_t dev) pci_dev_set_resources(dev); /* APIC */ - res = find_resource(dev, 0x14); + res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { - pci_write_config32(dev, 0x14, res->base); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); }

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New patch to review for coreboot: 6cbcddd ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14
by Jonathan A. Kollasch 11 Oct '13

11 Oct '13

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3962 -gerrit commit 6cbcddd45093e11a6922898e690f2ec6584f73f1 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 16:09:37 2013 -0500 ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14 Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c3f24bc..d8b699a 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -205,7 +205,7 @@ static void ck804_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) { - res = find_resource(dev, 0x14); /* IOAPIC */ + res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ if (res) { res->base = IO_APIC_ADDR; res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

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coreboot-gerrit October 2013