New patch to review for coreboot: 8f9135b Kratos-X1: Initial support for Micro Passion Kratos-X1
David Robinson (info@micropassion.co.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3964
-gerrit
commit 8f9135bcf4d07bc3581f91521a45a4c3f54a19cd Author: David Robinson info@micropassion.co.uk Date: Sat Oct 12 19:14:33 2013 +0100
Kratos-X1: Initial support for Micro Passion Kratos-X1
Initial support for Micro Passion Kratos-X1 PICO ITX single board computer featuring an AMD G-Series SOC (FT3). The configuration includes an example of soldered down DDR3 (No SPD). Removed non standard line endings.
Change-Id: I966b891a2fa562c5c29201cb7e7237b4ddfd107a Signed-off-by: David Robinson info@micropassion.co.uk --- src/mainboard/micropassion/Kconfig | 32 +- src/mainboard/micropassion/kratosx1/BiosCallOuts.c | 4 +- src/mainboard/micropassion/kratosx1/acpi/ide.asl | 250 -------------- src/mainboard/micropassion/kratosx1/acpi/sata.asl | 130 -------- src/mainboard/micropassion/kratosx1/devicetree.cb | 2 +- src/mainboard/micropassion/kratosx1/dsdt.asl | 2 +- src/mainboard/micropassion/kratosx1/get_bus_conf.c | 368 ++++++++++----------- src/mainboard/micropassion/kratosx1/romstage.c | 2 +- 8 files changed, 205 insertions(+), 585 deletions(-)
diff --git a/src/mainboard/micropassion/Kconfig b/src/mainboard/micropassion/Kconfig index 7045161..7dec41b 100755 --- a/src/mainboard/micropassion/Kconfig +++ b/src/mainboard/micropassion/Kconfig @@ -1,16 +1,16 @@ -if VENDOR_MICROPASSION - -choice - prompt "Mainboard model" - -config BOARD_MICROPASSION_KRATOSX1 - bool "KRATOS-X1" -endchoice - -source "src/mainboard/micropassion/kratosx1/Kconfig" - -config MAINBOARD_VENDOR - string - default "Micro Passion Ltd" - -endif # VENDOR_MICROPASSION +if VENDOR_MICROPASSION + +choice + prompt "Mainboard model" + +config BOARD_MICROPASSION_KRATOSX1 + bool "KRATOS-X1" +endchoice + +source "src/mainboard/micropassion/kratosx1/Kconfig" + +config MAINBOARD_VENDOR + string + default "Micro Passion Ltd" + +endif # VENDOR_MICROPASSION diff --git a/src/mainboard/micropassion/kratosx1/BiosCallOuts.c b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c index 6b62e0d..fb955a8 100755 --- a/src/mainboard/micropassion/kratosx1/BiosCallOuts.c +++ b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd + * Copyright (C) 2013 Micro Passion Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,7 +120,7 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_READ_SPD_PARAMS * Params = (AGESA_READ_SPD_PARAMS *) ConfigPtr;
printk(BIOS_DEBUG, "BiosReadSpd: %d %d %d\n", Params->SocketId, Params->MemChannelId, Params->DimmId); - + memcpy(Params->Buffer, SPD_2GB_1R8_1333, 256);
Status = AGESA_SUCCESS; diff --git a/src/mainboard/micropassion/kratosx1/acpi/ide.asl b/src/mainboard/micropassion/kratosx1/acpi/ide.asl deleted file mode 100755 index 853dc13..0000000 --- a/src/mainboard/micropassion/kratosx1/acpi/ide.asl +++ /dev/null @@ -1,250 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/micropassion/kratosx1/acpi/sata.asl b/src/mainboard/micropassion/kratosx1/acpi/sata.asl index 3d19222..5e4d1fe 100755 --- a/src/mainboard/micropassion/kratosx1/acpi/sata.asl +++ b/src/mainboard/micropassion/kratosx1/acpi/sata.asl @@ -18,133 +18,3 @@ */
/* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - _GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (_SB.P0PR) { - if (LGreater(_SB.P0IS,0)) { - sleep(32) - } - Notify(_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, _SB.P0PR) - } - - if (_SB.P1PR) { - if (LGreater(_SB.P1IS,0)) { - sleep(32) - } - Notify(_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, _SB.P1PR) - } - - if (_SB.P2PR) { - if (LGreater(_SB.P2IS,0)) { - sleep(32) - } - Notify(_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, _SB.P2PR) - } - - if (_SB.P3PR) { - if (LGreater(_SB.P3IS,0)) { - sleep(32) - } - Notify(_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, _SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/micropassion/kratosx1/devicetree.cb b/src/mainboard/micropassion/kratosx1/devicetree.cb index 451d290..28bc1a5 100755 --- a/src/mainboard/micropassion/kratosx1/devicetree.cb +++ b/src/mainboard/micropassion/kratosx1/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/micropassion/kratosx1/dsdt.asl b/src/mainboard/micropassion/kratosx1/dsdt.asl index 78d9bca..ee5e7ac 100755 --- a/src/mainboard/micropassion/kratosx1/dsdt.asl +++ b/src/mainboard/micropassion/kratosx1/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "MPL ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/micropassion/kratosx1/get_bus_conf.c b/src/mainboard/micropassion/kratosx1/get_bus_conf.c index 5413986..2147089 100755 --- a/src/mainboard/micropassion/kratosx1/get_bus_conf.c +++ b/src/mainboard/micropassion/kratosx1/get_bus_conf.c @@ -1,184 +1,184 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <string.h> -#include <stdint.h> -#include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" - -#define ACPI_MMIO_BASE 0xFED80000 - -/* Global variables for MB layouts and these will be shared by irqtable mptable - * and acpi_tables busnum is default. - */ -u8 bus_isa; -u8 bus_yangtze[3]; -u32 apicid_yangtze; - -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 bus_type[256]; -u32 sbdn_yangtze; - -static u32 get_bus_conf_done = 0; - -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif -void get_bus_conf(void) -{ - u32 apicid_base; - u32 status; - device_t pcidev; - u16 temp; - u32 * Ptr32; - u32 value; - - device_t dev; - int i, j; - - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); - - sbdn_yangtze = 0; - - for (i = 0; i < 3; i++) { - bus_yangtze[i] = 0; - } - - for (i = 0; i < 256; i++) { - bus_type[i] = 0; /* default ISA bus. */ - } - - bus_type[0] = 1; /* pci */ - - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; - - /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); - - if (dev) { - bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_yangtze[1]; j < bus_isa; j++) - bus_type[j] = 1; - } - - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); - if (dev) { - bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } - } - for (j = bus_yangtze[2]; j < bus_isa; j++) - bus_type[j] = 1; - - /* I/O APICs: APIC ID Version State Address */ - bus_isa = 10; - apicid_base = CONFIG_MAX_CPUS; - apicid_yangtze = apicid_base; - - - //Setup Ethernet LED Configuration - pcidev = dev_find_device(0x10EC, 0x8168, 0); - if (pcidev) - { - temp = pci_read_config16(pcidev, 0x10); - temp &= 0xFFFE; - printk(BIOS_DEBUG, "Found Realtek Ethernet controller with IO address: %x\n", temp); - outw (0xFF, (temp + 0x18)); - } - - Ptr32 = (u32 *) (ACPI_MMIO_BASE + 0xE00 + 0x00); //GPPClkCntrl - *Ptr32 &= ~0x0000; - *Ptr32 |= 0x430F; //Setup PCIe clocks based on clk_req lines - - //Setup PSI_L VID threshold - pcidev = dev_find_slot(0, PCI_DEVFN(0x18, 3)); - if (pcidev) - { - temp = pci_read_config16(pcidev, 0xA0); - temp &= 0xFF00; - temp |= 0xE2; - pci_write_config16(pcidev, 0xA0, temp); - } - -} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Micro Passion Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" + +#define ACPI_MMIO_BASE 0xFED80000 + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_yangtze[3]; +u32 apicid_yangtze; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_yangtze; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + device_t pcidev; + u16 temp; + u32 * Ptr32; + u32 value; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + + sbdn_yangtze = 0; + + for (i = 0; i < 3; i++) { + bus_yangtze[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; + + /* yangtze */ + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + + if (dev) { + bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_yangtze[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + if (dev) { + bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_yangtze[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_yangtze = apicid_base; + + + //Setup Ethernet LED Configuration + pcidev = dev_find_device(0x10EC, 0x8168, 0); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0x10); + temp &= 0xFFFE; + printk(BIOS_DEBUG, "Found Realtek Ethernet controller with IO address: %x\n", temp); + outw (0xFF, (temp + 0x18)); + } + + Ptr32 = (u32 *) (ACPI_MMIO_BASE + 0xE00 + 0x00); //GPPClkCntrl + *Ptr32 &= ~0x0000; + *Ptr32 |= 0x430F; //Setup PCIe clocks based on clk_req lines + + //Setup PSI_L VID threshold + pcidev = dev_find_slot(0, PCI_DEVFN(0x18, 3)); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0xA0); + temp &= 0xFF00; + temp |= 0xE2; + pci_write_config16(pcidev, 0xA0, temp); + } + +} diff --git a/src/mainboard/micropassion/kratosx1/romstage.c b/src/mainboard/micropassion/kratosx1/romstage.c index 51b6e86..7314223 100755 --- a/src/mainboard/micropassion/kratosx1/romstage.c +++ b/src/mainboard/micropassion/kratosx1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Micro Passion Ltd + * Copyright (C) 2013 Micro Passion Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by
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David Robinson