coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 98214de timestamps: Fix some lost timestamps for romstage
by Kyösti Mälkki 14 Oct '13

14 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3967 -gerrit commit 98214de60ebf9395d8bf62c2defe2cdb3ee3909d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 13:27:56 2013 +0300 timestamps: Fix some lost timestamps for romstage Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM, were lost with commit b766b1c7. Reason is variable ts_table was referencing CAR storage after CAR is torn doesn. Add use of car_get_var() / car_set_var() so the references go to migrated storage in CBMEM. Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/timestamp.c | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 8942649..678f38e 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -27,7 +27,7 @@ #define MAX_TIMESTAMPS 30 -static struct timestamp_table* ts_table CAR_GLOBAL = NULL; +static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 }; static void timestamp_stash(enum timestamp_id id, tsc_t ts_time); @@ -54,16 +54,18 @@ static void timestamp_real_init(tsc_t base) tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; - ts_table = tst; + car_set_var(ts_table_p, tst); } void timestamp_add(enum timestamp_id id, tsc_t ts_time) { struct timestamp_entry *tse; + struct timestamp_table *ts_table = NULL; if (!boot_cpu()) return; + ts_table = car_get_var(ts_table_p); if (!ts_table) { timestamp_stash(id, ts_time); return; @@ -90,30 +92,36 @@ struct timestamp_cache { static int timestamp_entries CAR_GLOBAL = 0; /** - * timestamp_stash() allows to temporarily cache time stamps. - * This is needed when time stamping before the CBMEM area - * is initialized. The function timestamp_sync() is used to - * write the time stamps to the CBMEM area. This is done in - * ram stage main() + * timestamp_stash() allows to temporarily cache timestamps. + * This is needed when timestamping before the CBMEM area + * is initialized. The function timestamp_do_sync() is used to + * write the timestamps to the CBMEM area and this is done as + * part of CAR migration for romstage, and in ramstage main(). */ static void timestamp_stash(enum timestamp_id id, tsc_t ts_time) { - if (timestamp_entries >= MAX_TIMESTAMP_CACHE) { + struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); + int ts_entries = car_get_var(timestamp_entries); + + if (ts_entries >= MAX_TIMESTAMP_CACHE) { printk(BIOS_ERR, "ERROR: failed to add timestamp to cache\n"); return; } - timestamp_cache[timestamp_entries].id = id; - timestamp_cache[timestamp_entries].time = ts_time; - timestamp_entries++; + ts_cache[ts_entries].id = id; + ts_cache[ts_entries].time = ts_time; + car_set_var(timestamp_entries, ++ts_entries); } static void timestamp_do_sync(void) { + struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); + int ts_entries = car_get_var(timestamp_entries); + int i; - for (i = 0; i < timestamp_entries; i++) - timestamp_add(timestamp_cache[i].id, timestamp_cache[i].time); - timestamp_entries = 0; + for (i = 0; i < ts_entries; i++) + timestamp_add(ts_cache[i].id, ts_cache[i].time); + car_set_var(timestamp_entries, 0); } void timestamp_init(tsc_t base) @@ -123,19 +131,19 @@ void timestamp_init(tsc_t base) #ifdef __PRE_RAM__ /* Copy of basetime, it is too early for CBMEM. */ - ts_basetime = base; + car_set_var(ts_basetime, base); #else struct timestamp_table* tst; /* Locate and use an already existing table. */ tst = cbmem_find(CBMEM_ID_TIMESTAMP); if (tst) { - ts_table = tst; + car_set_var(ts_table_p, tst); return; } /* Copy of basetime, may be too early for CBMEM. */ - ts_basetime = base; + car_set_var(ts_basetime, base); timestamp_real_init(base); #endif } @@ -146,12 +154,12 @@ void timestamp_reinit(void) return; #ifdef __PRE_RAM__ - timestamp_real_init(ts_basetime); + timestamp_real_init(car_get_var(ts_basetime)); #else - if (!ts_table) - timestamp_init(ts_basetime); + if (!car_get_var(ts_table_p)) + timestamp_init(car_get_var(ts_basetime)); #endif - if (ts_table) + if (car_get_var(ts_table_p)) timestamp_do_sync(); }

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Patch set updated for coreboot: 3c5427d timestamps: Fix some lost timestamps for romstage
by Kyösti Mälkki 14 Oct '13

14 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3967 -gerrit commit 3c5427d333f6ed75ef657198a16f217d11dd0129 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 13:27:56 2013 +0300 timestamps: Fix some lost timestamps for romstage Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM, were lost with commit b766b1c7. Reason is variable ts_table was referencing CAR storage after CAR is torn doesn. Add use of car_get_var() / car_set_var() so the references go to migrated storage in CBMEM. Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/timestamp.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 8942649..7cb9597 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -27,7 +27,7 @@ #define MAX_TIMESTAMPS 30 -static struct timestamp_table* ts_table CAR_GLOBAL = NULL; +static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 }; static void timestamp_stash(enum timestamp_id id, tsc_t ts_time); @@ -54,16 +54,18 @@ static void timestamp_real_init(tsc_t base) tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; - ts_table = tst; + car_set_var(ts_table_p, tst); } void timestamp_add(enum timestamp_id id, tsc_t ts_time) { struct timestamp_entry *tse; + struct timestamp_table *ts_table = NULL; if (!boot_cpu()) return; + ts_table = car_get_var(ts_table_p); if (!ts_table) { timestamp_stash(id, ts_time); return; @@ -90,11 +92,11 @@ struct timestamp_cache { static int timestamp_entries CAR_GLOBAL = 0; /** - * timestamp_stash() allows to temporarily cache time stamps. - * This is needed when time stamping before the CBMEM area - * is initialized. The function timestamp_sync() is used to - * write the time stamps to the CBMEM area. This is done in - * ram stage main() + * timestamp_stash() allows to temporarily cache timestamps. + * This is needed when timestamping before the CBMEM area + * is initialized. The function timestamp_do_sync() is used to + * write the timestamps to the CBMEM area and this is done as + * part of CAR migration for romstage, and in ramstage main(). */ static void timestamp_stash(enum timestamp_id id, tsc_t ts_time) @@ -123,19 +125,19 @@ void timestamp_init(tsc_t base) #ifdef __PRE_RAM__ /* Copy of basetime, it is too early for CBMEM. */ - ts_basetime = base; + car_set_var(ts_basetime, base); #else struct timestamp_table* tst; /* Locate and use an already existing table. */ tst = cbmem_find(CBMEM_ID_TIMESTAMP); if (tst) { - ts_table = tst; + car_set_var(ts_table_p, tst); return; } /* Copy of basetime, may be too early for CBMEM. */ - ts_basetime = base; + car_set_var(ts_basetime, base); timestamp_real_init(base); #endif } @@ -146,12 +148,12 @@ void timestamp_reinit(void) return; #ifdef __PRE_RAM__ - timestamp_real_init(ts_basetime); + timestamp_real_init(car_get_var(ts_basetime)); #else - if (!ts_table) - timestamp_init(ts_basetime); + if (!car_get_var(ts_table_p)) + timestamp_init(car_get_var(ts_basetime)); #endif - if (ts_table) + if (car_get_var(ts_table_p)) timestamp_do_sync(); }

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Patch merged into coreboot/master: f8bf5a1 Revert "CBMEM: Always have early initialisation"
by gerrit＠coreboot.org 14 Oct '13

14 Oct '13

the following patch was just integrated into master: commit f8bf5a10c599ef071998bbc3f16e9e3d7fcdb6eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 11 22:08:02 2013 +0300 Revert "CBMEM: Always have early initialisation" This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34. While things appeared to work, there were actually invalid references to CAR storage after CAR was torn down on boards without EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be restricted to boards that handle CAR migration properly. Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3968 for details. -gerrit

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Patch set updated for coreboot: ecd202d Makefile: Check $CC variable returned from xcompile is not empty.
by Andrew Wu 14 Oct '13

14 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3905 -gerrit commit ecd202d4dbc3ef88b42c063a2d70e92e5f3dd22a Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Sep 5 00:21:11 2013 +0800 Makefile: Check $CC variable returned from xcompile is not empty. If xcompile can't find out suitable GCC compiler for i386/armv7, it will not set $CC_i386/$CC_armv7 variable. Makefile sets $CC variable from xcompile, and will print strange error messages when executing $CC program if $CC is empty. Add checking to avoid this problem. If $CC is empty, also delete invalid .xcompile file, so Make can recreate this file next time. Change-Id: Ia8d481d76ca52f3351cb99f05779d06947161c5d Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 5 +++++ payloads/libpayload/Makefile | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..3b4d931 100644 --- a/Makefile +++ b/Makefile @@ -137,6 +137,11 @@ AR := $(AR_$(ARCH-y)) CFLAGS += $(CFLAGS_$(ARCH-y)) +ifeq ($(CC),) +$(shell rm .xcompile) +$(error no suitable GCC for $(ARCH-y)) +endif + LIBGCC_FILE_NAME := $(shell test -r `$(CC) -print-libgcc-file-name` && \ $(CC) -print-libgcc-file-name) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index bfa1abf..b319840 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -115,6 +115,11 @@ AR := $(AR_$(ARCH-y)) CFLAGS += $(CFLAGS_$(ARCH-y)) +ifeq ($(CC),) +$(shell rm .xcompile) +$(error no suitable GCC for $(ARCH-y)) +endif + LIBGCC_FILE_NAME := $(shell test -r `$(CC) -print-libgcc-file-name` && \ $(CC) -print-libgcc-file-name)

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Patch set updated for coreboot: d484d80 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
by Andrew Wu 14 Oct '13

14 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3896 -gerrit commit d484d8052775568055547d9e2a3561d3b2176635 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 1 + src/arch/x86/Makefile.inc | 1 + util/xcompile/xcompile | 1 + 3 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..b709d14 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ARCH-$(CONFIG_ARCH_X86) := i386 ifneq ($(INNER_SCANBUILD),y) CC := $(CC_$(ARCH-y)) endif +CPP := $(CPP_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) NM := $(NM_$(ARCH-y)) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b3b82b9..dee56c5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -427,6 +427,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index de6084d..5388889 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -117,6 +117,7 @@ report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm

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Patch merged into coreboot/master: cf18c85 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
by gerrit＠coreboot.org 14 Oct '13

14 Oct '13

the following patch was just integrated into master: commit cf18c856aafaaa2a7e5eaebf64a2d5c647e590e8 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 16:14:18 2013 -0500 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1 Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000 (that is, outside the range of bus 0 address space). This causes IOAPIC interrupts to fail to work under Linux. This issue was originally unnoticed by me when testing as sanity checking such as this is not done by NetBSD. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/3963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3963 for details. -gerrit

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Patch merged into coreboot/master: 948dede ck804: obtain stored IOAPIC address from allocator instead of register
by gerrit＠coreboot.org 14 Oct '13

14 Oct '13

the following patch was just integrated into master: commit 948dede9c5a3d67295c4b9528fd11e741459c116 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 15:52:30 2013 -0500 ck804: obtain stored IOAPIC address from allocator instead of register Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/3961 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3961 for details. -gerrit

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Patch merged into coreboot/master: b679525 ck804: obtain I/O APIC base address for ACPI MADT from allocator
by gerrit＠coreboot.org 14 Oct '13

14 Oct '13

the following patch was just integrated into master: commit b6795255389ffd2320307dc6848919049016dfbd Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Oct 11 14:58:39 2013 -0500 ck804: obtain I/O APIC base address for ACPI MADT from allocator Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/3960 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3960 for details. -gerrit

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New patch to review for coreboot: c54ea82 CBMEM: Define cbmem_top() just once for x86
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3972 -gerrit commit c54ea82919d0db8a6b6313a6db6c90dc6f80ce10 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 04:15:40 2013 +0300 CBMEM: Define cbmem_top() just once for x86 It is expected this will always be a casted get_top_of_ram() call on x86, no reason to do that under chipset. Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 10 +++++++++- src/mainboard/emulation/qemu-i440fx/memory.c | 8 -------- src/northbridge/intel/haswell/northbridge.c | 4 ++-- src/northbridge/intel/haswell/raminit.c | 6 ------ 4 files changed, 11 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 6a12263..bdc695c 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -55,4 +55,12 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) } #endif /* !__PRE_RAM__ */ -#endif +#else + +void *cbmem_top(void) +{ + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + return (void *)get_top_of_ram(); +} + +#endif /* DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 027deb9..a189d75 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -44,11 +44,3 @@ unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; } - -#if CONFIG_DYNAMIC_CBMEM -void *cbmem_top(void) -{ - /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ - return (void *)get_top_of_ram(); -} -#endif diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9f02734..ac61ca4 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -535,14 +535,14 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -void *cbmem_top(void) +unsigned long get_top_of_ram(void) { u32 reg; /* The top the reserve regions fall just below the TSEG region. */ reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - return (void *)(reg & ~((1 << 20) - 1)); + return (reg & ~((1 << 20) - 1)); } static void northbridge_enable(device_t dev) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index c1095a7..a90b360 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -202,12 +202,6 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -void *cbmem_top(void) -{ - /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ - return (void *)get_top_of_ram(); -} - unsigned long get_top_of_ram(void) { /*

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New patch to review for coreboot: 5e695b6 intel/i82371: Remove HAVE_ACPI_RESUME
by Kyösti Mälkki 13 Oct '13

13 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3971 -gerrit commit 5e695b6cfe20be34caaae73a95f098fa5b1710ba Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 23:06:09 2013 +0300 intel/i82371: Remove HAVE_ACPI_RESUME This is needed to apply a rule that get_top_of_ram() in romstage is required to select HAVE_ACPI_RESUME, otherwise chipset/board has no means to backup low memory to CBMEM on s3 resume. Only board affected is asus/p2b. Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82371eb/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 7e5109a..d91c8b7 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB bool - select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES config BOOTBLOCK_SOUTHBRIDGE_INIT string

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coreboot-gerrit October 2013