coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

1 participants
159 discussions

Patch set updated for coreboot: c1291d3 google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI`
by Ronald G. Minnich 24 Oct '13

24 Oct '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3987 -gerrit commit c1291d3497be29674e6d7c3f05cd1c39772ab9f4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Oct 21 20:23:35 2013 +0200 google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI` Make the declaration and use of it conditional on the ELOG_GSMI Kconfig variable. Change-Id: I2ef291d2f3e7d35545014e03ba8e0045da6050e5 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/parrot/smihandler.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a5f6ba2..ec2c9ea 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -94,7 +94,9 @@ static u8 mainboard_smi_ec(void) { u8 src; u32 pm1_cnt; +#if CONFIG_ELOG_GSMI static int battery_critical_logged; +#endif ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); @@ -106,8 +108,8 @@ static u8 mainboard_smi_ec(void) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); -#endif battery_critical_logged = 1; +#endif break; case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");

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New patch to review for coreboot: 1056907 dmp/vortex86ex: Add timeout for keyboard system flag checking.
by Andrew Wu 24 Oct '13

24 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3988 -gerrit commit 1056907696e02e3bf59e6d00b5b0a1e28e6e5df0 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit timeout, reload controller firmware code and try again. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..7ae39e8 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -25,6 +25,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> #include <string.h> +#include <delay.h> #include "arch/io.h" #include "chip.h" #include "southbridge.h" @@ -95,6 +96,9 @@ static const unsigned char irq_to_int_routing[16] = { #define POST_KBD_IS_READY 0x08 #define POST_KBD_FW_VERIFY_FAILURE 0x82 +/* keyboard controller system flag timeout */ +#define KBC_TIMEOUT_SYS_FLAG 400 + static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -140,15 +144,21 @@ static void upload_dmp_keyboard_firmware(struct device *dev) pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); } -static void kbc_wait_system_flag(void) +static int kbc_wait_system_flag(void) { /* wait keyboard controller ready by checking system flag * (status port bit 2). */ post_code(POST_KBD_CHK_READY); - while ((inb(0x64) & 0x4) == 0) { + u32 timeout; + for (timeout = KBC_TIMEOUT_SYS_FLAG; + timeout && ((inb(0x64) & 0x4) == 0); timeout--) + mdelay(1); + + if (!timeout) { + printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); } - post_code(POST_KBD_IS_READY); + return !!timeout; } static void pci_routing_fixup(struct device *dev) @@ -577,7 +587,13 @@ static void southbridge_init(struct device *dev) fix_cmos_rtc_time(); rtc_init(0); - kbc_wait_system_flag(); + /* Check keyboard controller ready. If timeout, reload firmware code + * and try again. + */ + while (!kbc_wait_system_flag()) { + upload_dmp_keyboard_firmware(dev); + } + post_code(POST_KBD_IS_READY); pc_keyboard_init(0); }

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Patch set updated for coreboot: 69a4c13 keyboard.c: fix coding style
by Andrew Wu 24 Oct '13

24 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3986 -gerrit commit 69a4c130dc284607f89014a7c8009bb2781fd651 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 23 20:47:20 2013 +0800 keyboard.c: fix coding style Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/drivers/pc80/keyboard.c | 100 ++++++++++++++++++++++++-------------------- 1 file changed, 55 insertions(+), 45 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 2888bcf..1cdad6d 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -19,7 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <console/console.h> #include <pc80/keyboard.h> #include <device/device.h> @@ -29,14 +28,14 @@ #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) // Keyboard Controller Commands -#define KBC_CMD_READ_COMMAND 0x20 // Read command byte -#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte -#define KBC_CMD_SELF_TEST 0xAA // Controller self-test -#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test +#define KBC_CMD_READ_COMMAND 0x20 // Read command byte +#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_SELF_TEST 0xAA // Controller self-test +#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test /* The Keyboard controller command byte * BIT | Description @@ -52,14 +51,14 @@ */ // Keyboard Controller Replies -#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded +#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded // // Keyboard Replies // -#define KBD_REPLY_POR 0xAA // Power on reset -#define KBD_REPLY_ACK 0xFA // Command ACK -#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again +#define KBD_REPLY_POR 0xAA // Power on reset +#define KBD_REPLY_ACK 0xFA // Command ACK +#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again /* Wait 400ms for keyboard controller answers */ #define KBC_TIMEOUT_IN_MS 400 @@ -67,43 +66,43 @@ static int kbc_input_buffer_empty(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) mdelay(1); - } - if (!timeout) { - printk(BIOS_WARNING, "Unexpected Keyboard controller input buffer full\n"); - } + if (!timeout) + printk(BIOS_WARNING, + "Unexpected Keyboard controller input buffer full\n"); return !!timeout; } - static int kbc_output_buffer_full(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) mdelay(1); - } - if (!timeout) { - printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n"); - } + if (!timeout) + printk(BIOS_INFO, + "Keyboard controller output buffer result timeout\n"); return !!timeout; } - static int kbc_cleanup_buffers(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { mdelay(1); inb(KBD_DATA); } if (!timeout) { - printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n"); + printk(BIOS_ERR, + "Couldn't cleanup the keyboard controller buffers\n"); printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", - KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); + KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); } return !!timeout; @@ -133,7 +132,7 @@ static int kbc_self_test(void) if (self_test != 0x55) { printk(BIOS_ERR, "Keyboard Controller self-test failed: 0x%x\n", - self_test); + self_test); return 0; } @@ -153,7 +152,7 @@ static int kbc_self_test(void) if (self_test != 0x00) { printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n", - self_test); + self_test); return 0; } @@ -166,19 +165,21 @@ static u8 send_keyboard(u8 command) u8 resend = 10; do { - if (!kbc_input_buffer_empty()) return 0; + if (!kbc_input_buffer_empty()) + return 0; outb(command, KBD_DATA); /* the reset command takes much longer then normal commands and * even worse, some keyboards do send the ACK _after_ doing the * reset */ if (command == 0xFF) { u8 retries; - for (retries = 9; retries && !kbc_output_buffer_full(); retries--) - ; + for (retries = 9; retries && !kbc_output_buffer_full(); + retries--) ; } if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Could not send keyboard command %02x\n", - command); + printk(BIOS_ERR, + "Could not send keyboard command %02x\n", + command); return 0; } regval = inb(KBD_DATA); @@ -201,9 +202,11 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) return; /* Enable keyboard interface - No IRQ */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ if (!kbc_input_buffer_empty()) { printk(BIOS_INFO, "Timeout while enabling keyboard\n"); @@ -211,7 +214,8 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) } /* clean up any junk that might have been in the keyboard */ - if (!kbc_cleanup_buffers()) return; + if (!kbc_cleanup_buffers()) + return; /* reset keyboard and self test (keyboard side) */ regval = send_keyboard(0xFF); @@ -227,8 +231,7 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) } /* the reset command takes some time, so wait a little longer */ - for (retries = 9; retries && !kbc_output_buffer_full(); retries--) - ; + for (retries = 9; retries && !kbc_output_buffer_full(); retries--) ; if (!kbc_output_buffer_full()) { printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); @@ -237,7 +240,8 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) regval = inb(KBD_DATA); if (regval != 0xAA) { - printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval); + printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", + regval); return; } @@ -256,20 +260,24 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) /* Set scancode command */ regval = send_keyboard(0xF0); if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval); + printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", + regval); return; } /* Set scancode mode 2 */ regval = send_keyboard(0x02); if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval); + printk(BIOS_ERR, + "Keyboard set scancode mode failed ACK: 0x%x\n", regval); return; } /* All is well - enable keyboard interface */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during keyboard enable\n"); @@ -296,10 +304,12 @@ void set_kbc_ps2_mode(void) return; /* Support PS/2 mode */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0xcb, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x01, KBD_DATA); kbc_cleanup_buffers();

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New patch to review for coreboot: e773d51 google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI`
by Paul Menzel 23 Oct '13

23 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3987 -gerrit commit e773d51e9f7988aef065a99d5fece932d6f28ce7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Oct 21 20:23:35 2013 +0200 google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI` Removing `-Wno-unused-but-set-variable` from `CFLAGS` results in the following error. CC mainboard/google/parrot/smihandler.smm.o src/mainboard/google/parrot/smihandler.c: In function 'mainboard_smi_ec': src/mainboard/google/parrot/smihandler.c:97:13: error: variable 'battery_critical_logged' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors As the variable is only used, when the Kconfig variable `ELOG_GSMI` is not zero, only declare and set it in that case. Change-Id: I2ef291d2f3e7d35545014e03ba8e0045da6050e5 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/parrot/smihandler.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a5f6ba2..ec2c9ea 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -94,7 +94,9 @@ static u8 mainboard_smi_ec(void) { u8 src; u32 pm1_cnt; +#if CONFIG_ELOG_GSMI static int battery_critical_logged; +#endif ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); @@ -106,8 +108,8 @@ static u8 mainboard_smi_ec(void) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); -#endif battery_critical_logged = 1; +#endif break; case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");

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New patch to review for coreboot: 6d52aad keyboard.c: fix coding style
by Andrew Wu 23 Oct '13

23 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3986 -gerrit commit 6d52aadc952163ea027571732696e85af15dd3b0 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 23 20:47:20 2013 +0800 keyboard.c: fix coding style Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/drivers/pc80/keyboard.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 2888bcf..99f1a12 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -29,8 +29,8 @@ #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) // Keyboard Controller Commands #define KBC_CMD_READ_COMMAND 0x20 // Read command byte @@ -67,13 +67,11 @@ static int kbc_input_buffer_empty(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) mdelay(1); - } - if (!timeout) { + if (!timeout) printk(BIOS_WARNING, "Unexpected Keyboard controller input buffer full\n"); - } return !!timeout; } @@ -81,13 +79,11 @@ static int kbc_input_buffer_empty(void) static int kbc_output_buffer_full(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) mdelay(1); - } - if (!timeout) { + if (!timeout) printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n"); - } return !!timeout; } @@ -95,7 +91,7 @@ static int kbc_output_buffer_full(void) static int kbc_cleanup_buffers(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { mdelay(1); inb(KBD_DATA); }

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Patch merged into coreboot/master: 1ce4860 vortex86ex: Defer checking PS/2 keyboard controller system flag
by gerrit＠coreboot.org 22 Oct '13

22 Oct '13

the following patch was just integrated into master: commit 1ce4860405d995585d08350481932238ee2f8c4a Author: Andrew Wu <arw(a)dmp.com.tw> Date: Sat Oct 19 01:33:08 2013 +0800 vortex86ex: Defer checking PS/2 keyboard controller system flag Don't check keyboard controller system flag until before calling pc_keyboard_init(). This makes waiting time shorter. Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3958 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3958 for details. -gerrit

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Patch set updated for coreboot: 3e359e8 dmp/vortex86ex: Initialize I2C controller base address/IRQ
by Ronald G. Minnich 22 Oct '13

22 Oct '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit 3e359e8876c2c956d17f53fe813eb72fba6ff6ed Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 16 13:08:30 2013 +0800 dmp/vortex86ex: Initialize I2C controller base address/IRQ Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/Kconfig | 5 +++++ src/southbridge/dmp/vortex86ex/southbridge.c | 12 ++++++++++++ src/southbridge/dmp/vortex86ex/southbridge.h | 1 + 3 files changed, 18 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 723a251..b1db0dc 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -50,6 +50,11 @@ config ID_SECTION_OFFSET hex default 0x4800 +# SPI I/O base address control. +config I2C_BASE + hex + default 0xfb00 + # ROM Strap PLL config setting : choice diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d8914c0..d431c1c 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = { #define PIDE_IRQ 5 #define SPI1_IRQ 10 +#define I2C0_IRQ 10 #define MOTOR_IRQ 11 /* RT0-3 IRQs. */ @@ -418,6 +419,16 @@ static void ex_sb_uart_init(struct device *dev) //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0); } +static void i2c_init(struct device *dev) +{ + u8 mapped_irq = irq_to_int_routing[I2C0_IRQ]; + u32 cfg = 0; + cfg |= 1 << 31; // UE = enabled. + cfg |= (mapped_irq << 16); // IIRT0. + cfg |= CONFIG_I2C_BASE; // UIOA. + pci_write_config32(dev, SB_REG_II2CCR, cfg); +} + static int get_rtc_update_in_progress(void) { if (cmos_read(RTC_REG_A) & RTC_UIP) @@ -566,6 +577,7 @@ static void southbridge_init(struct device *dev) if (dev->device == 0x6011) { ex_sb_gpio_init(dev); ex_sb_uart_init(dev); + i2c_init(dev); } pci_routing_fixup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 0cc28fa..316d30a 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -36,6 +36,7 @@ #define SB_REG_IPFCR 0xc0 #define SB_REG_FRWPR 0xc4 #define SB_REG_STRAP 0xce +#define SB_REG_II2CCR 0xd4 #define SB1 PCI_DEV(0, 7, 1) #define SB1_REG_EXT_PIRQ_ROUTE2 0xb4

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Patch set updated for coreboot: 22d57b3 southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`
by Ronald G. Minnich 22 Oct '13

22 Oct '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3985 -gerrit commit 22d57b3afc4a46be4b869d411b5855f4630df2fd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 20 00:41:28 2013 +0200 southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3` Change-Id: I6bb652419a54b7b7190e417346581f38335425ae Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/via/vt8237r/ctrl.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c index 78a15e3..e61b8f2 100644 --- a/src/southbridge/via/vt8237r/ctrl.c +++ b/src/southbridge/via/vt8237r/ctrl.c @@ -29,7 +29,7 @@ static void vt8237_cfg(struct device *dev) { - u8 regm, regm3; + u8 regm; device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, @@ -80,8 +80,7 @@ static void vt8237_cfg(struct device *dev) regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm); - // FIXME is this really supposed to be regm3? - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm = pci_read_config8(devfun3, 0x82);/* Shadow page E */ pci_write_config8(dev, 0x64, regm); regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */

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Patch merged into coreboot/master: ac16405 usbdebug: Fix boards without EARLY_CBMEM_INIT
by gerrit＠coreboot.org 22 Oct '13

22 Oct '13

the following patch was just integrated into master: commit ac164057993e9edbfe78537efbbc9ef5f75cd67c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 11 21:14:59 2013 +0300 usbdebug: Fix boards without EARLY_CBMEM_INIT The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3983 for details. -gerrit

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Patch set updated for coreboot: b6591b3 dmp/vortex86ex: Initialize I2C controller base address/IRQ
by Andrew Wu 22 Oct '13

22 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit b6591b3726e56e9d8e51115945dfeba3b7ef35db Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 16 13:08:30 2013 +0800 dmp/vortex86ex: Initialize I2C controller base address/IRQ Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/Kconfig | 5 +++++ src/southbridge/dmp/vortex86ex/southbridge.c | 12 ++++++++++++ src/southbridge/dmp/vortex86ex/southbridge.h | 1 + 3 files changed, 18 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 723a251..b1db0dc 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -50,6 +50,11 @@ config ID_SECTION_OFFSET hex default 0x4800 +# SPI I/O base address control. +config I2C_BASE + hex + default 0xfb00 + # ROM Strap PLL config setting : choice diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d8914c0..d431c1c 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = { #define PIDE_IRQ 5 #define SPI1_IRQ 10 +#define I2C0_IRQ 10 #define MOTOR_IRQ 11 /* RT0-3 IRQs. */ @@ -418,6 +419,16 @@ static void ex_sb_uart_init(struct device *dev) //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0); } +static void i2c_init(struct device *dev) +{ + u8 mapped_irq = irq_to_int_routing[I2C0_IRQ]; + u32 cfg = 0; + cfg |= 1 << 31; // UE = enabled. + cfg |= (mapped_irq << 16); // IIRT0. + cfg |= CONFIG_I2C_BASE; // UIOA. + pci_write_config32(dev, SB_REG_II2CCR, cfg); +} + static int get_rtc_update_in_progress(void) { if (cmos_read(RTC_REG_A) & RTC_UIP) @@ -566,6 +577,7 @@ static void southbridge_init(struct device *dev) if (dev->device == 0x6011) { ex_sb_gpio_init(dev); ex_sb_uart_init(dev); + i2c_init(dev); } pci_routing_fixup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 0cc28fa..316d30a 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -36,6 +36,7 @@ #define SB_REG_IPFCR 0xc0 #define SB_REG_FRWPR 0xc4 #define SB_REG_STRAP 0xce +#define SB_REG_II2CCR 0xd4 #define SB1 PCI_DEV(0, 7, 1) #define SB1_REG_EXT_PIRQ_ROUTE2 0xb4

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coreboot-gerrit October 2013