coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ffc3836 Add a KEEP_BOOT_COUNT Kconfig option.
by Denis Carikli 27 Oct '13

27 Oct '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3990 -gerrit commit ffc383684079d60e7d20403ef7c3877d580c57b4 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Oct 21 01:56:47 2013 +0200 Add a KEEP_BOOT_COUNT Kconfig option. The use case of that option is to inform coreboot (trough the nvram) at the next boot, that the computer could not fully boot to boot to an usable state. In that case, the boot count is incremented by one. Previously there was no way to tell coreboot that the computer really booted successfully, because it was assumed that if set_boot_successful was called in ramstage, then the computer would have booted successfully. However many things can go wrong after that point, for instance the payload could fail to boot, or the operating system's kernel could fail to boot too, due to the wrong configurations passed to it by coreboot and the payload. Change-Id: I01af053455eb6bd2f7a4f9d37e8c234ba8d55250 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/Kconfig | 7 +++++++ src/lib/fallback_boot.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 10f8c18..1ccc818 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,6 +47,13 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config KEEP_BOOT_COUNT + bool "Keep boot count" + depends on PC80_SYSTEM + help + If enabled, the boot count is not reset anymore in the ramstage. + This delegates that task to the software running after the ramstage. + config ALT_CBFS_LOAD_PAYLOAD bool "Use alternative cbfs_load_payload() implementation." default n diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index b956c94..7f5db63 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -3,7 +3,7 @@ #include <watchdog.h> #include <arch/io.h> -#if CONFIG_PC80_SYSTEM +#if CONFIG_PC80_SYSTEM && !CONFIG_KEEP_BOOT_COUNT #include <pc80/mc146818rtc.h> static void set_boot_successful(void)

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New patch to review for coreboot: acb6e27 roda/rk9: Remove unused HAVE_ACPI_RESUME
by Kyösti Mälkki 27 Oct '13

27 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3995 -gerrit commit acb6e27d0fa74cff327b45262c264ad2fdef0dd3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 20:41:57 2013 +0300 roda/rk9: Remove unused HAVE_ACPI_RESUME Change-Id: I154f1a97bc1102af80310d9820aa2bd3042ee681 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/roda/rk9/Kconfig | 1 - src/mainboard/roda/rk9/romstage.c | 19 ------------------- 2 files changed, 20 deletions(-) diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 59ae455..54caba7 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES - #select HAVE_ACPI_RESUME select EC_ACPI select HAVE_OPTION_TABLE diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 075790d..79d19e0 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -183,25 +183,6 @@ void main(unsigned long bist) init_iommu(); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_reinit() { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } -#endif printk(BIOS_SPEW, "exit main()\n"); }

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New patch to review for coreboot: c668096 intel/i945 boards: Add EARLY_CBMEM_INIT
by Kyösti Mälkki 27 Oct '13

27 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3994 -gerrit commit c668096b58dc50a51de63ddd810544af4f6b5cc7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 20:41:57 2013 +0300 intel/i945 boards: Add EARLY_CBMEM_INIT Inspired by commits ac6ea04b and 4560ca50 that enabled this feature for lenovo/x60 and lenovo/t60 with i945 chipset. Change-Id: Ia04f58b8c3769b5734708c6a338bb80c13c5aeba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/getac/p470/romstage.c | 8 +++++--- src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/ibase/mb899/romstage.c | 8 +++++--- src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/intel/d945gclf/romstage.c | 8 +++++--- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 8 +++++--- src/mainboard/roda/rk886ex/Kconfig | 1 + src/mainboard/roda/rk886ex/romstage.c | 8 +++++--- 10 files changed, 30 insertions(+), 15 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 3fdf6f7..db42233 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_FDC37N972 select SUPERIO_SMSC_SIO10N268 select EC_ACPI + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index f4e43e5..87af8ca 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -263,12 +264,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -357,11 +357,13 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 36353b3..72b916f 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index b059a57..222c376 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -221,12 +222,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -311,11 +311,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 0a9de1a..b676eb6 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 248aa3b..166743f 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include "superio/smsc/lpc47m15x/lpc47m15x.h" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -182,12 +183,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -269,11 +269,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index e8b7225..29d4da4 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 324f442..1875a10 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <string.h> #include <lib.h> +#include <cbmem.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -314,12 +315,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -410,11 +410,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 2113deb..365980e 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index cb141f9..e08c1c0 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -249,12 +250,11 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -346,11 +346,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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New patch to review for coreboot: 4065d0c CBMEM intel: Define get_top_of_ram() once per chipset
by Kyösti Mälkki 27 Oct '13

27 Oct '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3993 -gerrit commit 4065d0cfb95b23d1267867511389135114b47852 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 15 17:19:41 2013 +0300 CBMEM intel: Define get_top_of_ram() once per chipset Only have one definition of get_top_of_ram() function and compile it using __SIMPLE_DEVICE__ for both romstage and ramstage. Implemented like this on intel/northbridge/gm45 already. This also adds get_top_of_ram() to i945 ramstage. Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/haswell/Makefile.inc | 2 + src/northbridge/intel/haswell/northbridge.c | 10 ----- src/northbridge/intel/haswell/ram_calc.c | 35 +++++++++++++++ src/northbridge/intel/haswell/raminit.c | 10 ----- src/northbridge/intel/i945/Makefile.inc | 2 + src/northbridge/intel/i945/ram_calc.c | 57 +++++++++++++++++++++++++ src/northbridge/intel/i945/raminit.c | 33 -------------- src/northbridge/intel/sandybridge/Makefile.inc | 2 + src/northbridge/intel/sandybridge/northbridge.c | 7 --- src/northbridge/intel/sandybridge/ram_calc.c | 31 ++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 7 --- 11 files changed, 129 insertions(+), 67 deletions(-) diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2ac85e..5752a99 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,12 +17,14 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ac61ca4..9440999 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -535,16 +535,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -unsigned long get_top_of_ram(void) -{ - u32 reg; - - /* The top the reserve regions fall just below the TSEG region. */ - reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - - return (reg & ~((1 << 20) - 1)); -} - static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c new file mode 100644 index 0000000..99e7d67 --- /dev/null +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "haswell.h" + +unsigned long get_top_of_ram(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignement. + */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom & ~((1 << 20) - 1); +} diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index a90b360..171f738 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -201,13 +201,3 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } - -unsigned long get_top_of_ram(void) -{ - /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignement. - */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); -} diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 92a8849..67643eb 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -17,10 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c new file mode 100644 index 0000000..4ece540 --- /dev/null +++ b/src/northbridge/intel/i945/ram_calc.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "i945.h" + +unsigned long get_top_of_ram(void) +{ + u32 tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b50f1d8..f4cba94 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3184,36 +3184,3 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) sdram_setup_processor_side(); } - -unsigned long get_top_of_ram(void) -{ - u32 tom; - - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { - /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - } else { - tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; - } - - /* if TSEG enabled subtract size */ - switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { - case 0x01: - /* 1MB TSEG */ - tom -= 0x10000; - break; - case 0x03: - /* 2MB TSEG */ - tom -= 0x20000; - break; - case 0x05: - /* 8MB TSEG */ - tom -= 0x80000; - break; - default: - /* TSEG either disabled or invalid */ - break; - } - return (unsigned long) tom; -} - diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index be07e93..2c2e05a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,12 +17,14 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a03b8a6..7db9301 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,13 +51,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); - return (unsigned long) tom; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c new file mode 100644 index 0000000..3693a07 --- /dev/null +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "sandybridge.h" + +unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3b321d7..6fca4a0 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -304,10 +304,3 @@ void sdram_initialize(struct pei_data *pei_data) if (pei_data->boot_mode != 2) save_mrc_data(pei_data); } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; -}

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New patch to review for coreboot: a294976 lenovo/x60: export reboot_bits nvram configuration.
by Denis Carikli 26 Oct '13

26 Oct '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3992 -gerrit commit a294976f365be855f08b175c25a8e285b3f4f6e0 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Oct 26 22:35:46 2013 +0200 lenovo/x60: export reboot_bits nvram configuration. This permits any software running after the ramstage to tell coreboot that the boot was successfull. Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/cmos.layout | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index ab51a84..d622dcd 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -71,7 +71,7 @@ entries # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 385 1 e 4 last_boot -388 4 r 0 reboot_bits +388 4 e 10 reboot_bits #390 2 r 0 unused? # ----------------------------------------------------------------- @@ -146,6 +146,22 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 0 +10 1 1 +10 2 2 +10 3 3 +10 4 4 +10 5 5 +10 6 6 +10 7 7 +10 8 8 +10 9 9 +10 10 10 +10 11 11 +10 12 12 +10 13 13 +10 14 14 +10 15 15 # ----------------------------------------------------------------- checksums

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New patch to review for coreboot: 22bfe53 lenovo/x60: Require only one failed boot to switch to fallback in X86_BOOTBLOCK_NORMAL mode.
by Denis Carikli 26 Oct '13

26 Oct '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3991 -gerrit commit 22bfe53dd508dd05612f0d4cfd52f804226d2c29 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Oct 20 23:37:35 2013 +0200 lenovo/x60: Require only one failed boot to switch to fallback in X86_BOOTBLOCK_NORMAL mode. src/arch/x86/Kconfig defines MAX_REBOOT_CNT as 3. If that value is not overrided, then the Lenovo X60 coreboot image gets it too. At the end of a successfull boot, with CONFIG_KEEP_BOOT_COUNT, the Lenovo X60 increments its reboot_bits cmos option by one. In case of a failed boot, the user probably doesn't know that coreboot will only switch to fallback after 3 failed boots, and will act as if the laptop will not boot anymore with its current coreboot image. Change-Id: I746df11c933dfe62e01e1591479ca96a84907dc0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 72aeef8..90d472c 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -54,6 +54,10 @@ config MAX_CPUS int default 2 +config MAX_REBOOT_CNT + int + default 1 + config MAINBOARD_SMBIOS_MANUFACTURER string default "LENOVO"

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New patch to review for coreboot: e42a187 Add a KEEP_BOOT_COUNT Kconfig option.
by Denis Carikli 26 Oct '13

26 Oct '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3990 -gerrit commit e42a1878c226e98550034dd3d4005592d888991a Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Oct 21 01:56:47 2013 +0200 Add a KEEP_BOOT_COUNT Kconfig option. The use case of that option is to inform coreboot (trough the nvram) at the next boot, that the computer could not fully boot to boot to an usable state. In that case, the boot count is incremented by one. Previously there was no way to tell coreboot that the computer really booted successfully, because it was assumed that if set_boot_successful was called in ramstage, then the computer would have booted successfully. However many things can go wrong after that point, for instance the payload could fail to boot, or the operating system's kernel could fail to boot too, due to the wrong configurations passed to it by coreboot and the payload. Change-Id: I01af053455eb6bd2f7a4f9d37e8c234ba8d55250 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/Kconfig | 7 +++++++ src/lib/fallback_boot.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 10f8c18..1ccc818 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,6 +47,13 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config KEEP_BOOT_COUNT + bool "Keep boot count" + depends on PC80_SYSTEM + help + If enabled, the boot count is not reset anymore in the ramstage. + This delegates that task to the software running after the ramstage. + config ALT_CBFS_LOAD_PAYLOAD bool "Use alternative cbfs_load_payload() implementation." default n diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index b956c94..7f5db63 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -3,7 +3,7 @@ #include <watchdog.h> #include <arch/io.h> -#if CONFIG_PC80_SYSTEM +#if CONFIG_PC80_SYSTEM && !CONFIG_KEEP_BOOT_COUNT #include <pc80/mc146818rtc.h> static void set_boot_successful(void)

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Patch set updated for coreboot: 42bbb02 dmp/vortex86ex: Add timeout for keyboard system flag checking.
by Andrew Wu 26 Oct '13

26 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3988 -gerrit commit 42bbb0281828617113975c691f9abe64f6c21cea Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..c424b51 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -25,6 +25,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> #include <string.h> +#include <delay.h> #include "arch/io.h" #include "chip.h" #include "southbridge.h" @@ -95,6 +96,9 @@ static const unsigned char irq_to_int_routing[16] = { #define POST_KBD_IS_READY 0x08 #define POST_KBD_FW_VERIFY_FAILURE 0x82 +/* keyboard controller system flag timeout : 400 ms*/ +#define KBC_TIMEOUT_SYS_FLAG 400 + static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -140,15 +144,21 @@ static void upload_dmp_keyboard_firmware(struct device *dev) pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); } -static void kbc_wait_system_flag(void) +static int kbc_wait_system_flag(void) { /* wait keyboard controller ready by checking system flag * (status port bit 2). */ post_code(POST_KBD_CHK_READY); - while ((inb(0x64) & 0x4) == 0) { + u32 timeout; + for (timeout = KBC_TIMEOUT_SYS_FLAG; + timeout && ((inb(0x64) & 0x4) == 0); timeout--) + mdelay(1); + + if (!timeout) { + printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); } - post_code(POST_KBD_IS_READY); + return !!timeout; } static void pci_routing_fixup(struct device *dev) @@ -577,7 +587,13 @@ static void southbridge_init(struct device *dev) fix_cmos_rtc_time(); rtc_init(0); - kbc_wait_system_flag(); + /* Check keyboard controller ready. If timeout, reload firmware code + * and try again. + */ + while (!kbc_wait_system_flag()) { + upload_dmp_keyboard_firmware(dev); + } + post_code(POST_KBD_IS_READY); pc_keyboard_init(0); }

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Patch set updated for coreboot: a51b776 keyboard.c: fix coding style with indent
by Paul Menzel 26 Oct '13

26 Oct '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3986 -gerrit commit a51b77677391d3c0bd574b96ca9937d9dd59e580 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 23 20:47:20 2013 +0800 keyboard.c: fix coding style with indent Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/drivers/pc80/keyboard.c | 100 ++++++++++++++++++++++++-------------------- 1 file changed, 55 insertions(+), 45 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 2888bcf..1cdad6d 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -19,7 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <console/console.h> #include <pc80/keyboard.h> #include <device/device.h> @@ -29,14 +28,14 @@ #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) // Keyboard Controller Commands -#define KBC_CMD_READ_COMMAND 0x20 // Read command byte -#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte -#define KBC_CMD_SELF_TEST 0xAA // Controller self-test -#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test +#define KBC_CMD_READ_COMMAND 0x20 // Read command byte +#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_SELF_TEST 0xAA // Controller self-test +#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test /* The Keyboard controller command byte * BIT | Description @@ -52,14 +51,14 @@ */ // Keyboard Controller Replies -#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded +#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded // // Keyboard Replies // -#define KBD_REPLY_POR 0xAA // Power on reset -#define KBD_REPLY_ACK 0xFA // Command ACK -#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again +#define KBD_REPLY_POR 0xAA // Power on reset +#define KBD_REPLY_ACK 0xFA // Command ACK +#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again /* Wait 400ms for keyboard controller answers */ #define KBC_TIMEOUT_IN_MS 400 @@ -67,43 +66,43 @@ static int kbc_input_buffer_empty(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) mdelay(1); - } - if (!timeout) { - printk(BIOS_WARNING, "Unexpected Keyboard controller input buffer full\n"); - } + if (!timeout) + printk(BIOS_WARNING, + "Unexpected Keyboard controller input buffer full\n"); return !!timeout; } - static int kbc_output_buffer_full(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) mdelay(1); - } - if (!timeout) { - printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n"); - } + if (!timeout) + printk(BIOS_INFO, + "Keyboard controller output buffer result timeout\n"); return !!timeout; } - static int kbc_cleanup_buffers(void) { u32 timeout; - for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { mdelay(1); inb(KBD_DATA); } if (!timeout) { - printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n"); + printk(BIOS_ERR, + "Couldn't cleanup the keyboard controller buffers\n"); printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", - KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); + KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); } return !!timeout; @@ -133,7 +132,7 @@ static int kbc_self_test(void) if (self_test != 0x55) { printk(BIOS_ERR, "Keyboard Controller self-test failed: 0x%x\n", - self_test); + self_test); return 0; } @@ -153,7 +152,7 @@ static int kbc_self_test(void) if (self_test != 0x00) { printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n", - self_test); + self_test); return 0; } @@ -166,19 +165,21 @@ static u8 send_keyboard(u8 command) u8 resend = 10; do { - if (!kbc_input_buffer_empty()) return 0; + if (!kbc_input_buffer_empty()) + return 0; outb(command, KBD_DATA); /* the reset command takes much longer then normal commands and * even worse, some keyboards do send the ACK _after_ doing the * reset */ if (command == 0xFF) { u8 retries; - for (retries = 9; retries && !kbc_output_buffer_full(); retries--) - ; + for (retries = 9; retries && !kbc_output_buffer_full(); + retries--) ; } if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Could not send keyboard command %02x\n", - command); + printk(BIOS_ERR, + "Could not send keyboard command %02x\n", + command); return 0; } regval = inb(KBD_DATA); @@ -201,9 +202,11 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) return; /* Enable keyboard interface - No IRQ */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ if (!kbc_input_buffer_empty()) { printk(BIOS_INFO, "Timeout while enabling keyboard\n"); @@ -211,7 +214,8 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) } /* clean up any junk that might have been in the keyboard */ - if (!kbc_cleanup_buffers()) return; + if (!kbc_cleanup_buffers()) + return; /* reset keyboard and self test (keyboard side) */ regval = send_keyboard(0xFF); @@ -227,8 +231,7 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) } /* the reset command takes some time, so wait a little longer */ - for (retries = 9; retries && !kbc_output_buffer_full(); retries--) - ; + for (retries = 9; retries && !kbc_output_buffer_full(); retries--) ; if (!kbc_output_buffer_full()) { printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); @@ -237,7 +240,8 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) regval = inb(KBD_DATA); if (regval != 0xAA) { - printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval); + printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", + regval); return; } @@ -256,20 +260,24 @@ void pc_keyboard_init(struct pc_keyboard *keyboard) /* Set scancode command */ regval = send_keyboard(0xF0); if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval); + printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", + regval); return; } /* Set scancode mode 2 */ regval = send_keyboard(0x02); if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval); + printk(BIOS_ERR, + "Keyboard set scancode mode failed ACK: 0x%x\n", regval); return; } /* All is well - enable keyboard interface */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during keyboard enable\n"); @@ -296,10 +304,12 @@ void set_kbc_ps2_mode(void) return; /* Support PS/2 mode */ - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0xcb, KBD_COMMAND); - if (!kbc_input_buffer_empty()) return; + if (!kbc_input_buffer_empty()) + return; outb(0x01, KBD_DATA); kbc_cleanup_buffers();

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New patch to review for coreboot: 8e5493f dmp/vortex86ex: Move DMP specific POST code defines into one file
by Andrew Wu 25 Oct '13

25 Oct '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3989 -gerrit commit 8e5493f00074315ba95107bcd6681fc57710889c Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Oct 25 16:22:57 2013 +0800 dmp/vortex86ex: Move DMP specific POST code defines into one file Move into src/mainboard/dmp/vortex86ex/dmp_post_code.h Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/dmp_post_code.h | 33 ++++++++++++++++++++++++++++ src/mainboard/dmp/vortex86ex/romstage.c | 10 +++------ src/southbridge/dmp/vortex86ex/southbridge.c | 15 +++++-------- 3 files changed, 41 insertions(+), 17 deletions(-) diff --git a/src/mainboard/dmp/vortex86ex/dmp_post_code.h b/src/mainboard/dmp/vortex86ex/dmp_post_code.h new file mode 100644 index 0000000..6658ce8 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/dmp_post_code.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DMP_POST_CODE_H +#define DMP_POST_CODE_H + +/* DMP Vortex86EX specific POST codes */ + +#define POST_DMP_KBD_FW_UPLOAD 0x06 +#define POST_DMP_KBD_CHK_READY 0x07 +#define POST_DMP_KBD_IS_READY 0x08 +#define POST_DMP_KBD_FW_VERIFY_ERR 0x82 +#define POST_DMP_ID_ERR 0x85 +#define POST_DMP_DRAM_TEST_ERR 0x86 +#define POST_DMP_DRAM_SIZING_ERR 0x77 + +#endif /* DMP_POST_CODE_H*/ diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index 72fbde0..ec3e581 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -27,6 +27,7 @@ #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" #include "northbridge/dmp/vortex86ex/raminit.c" +#include "dmp_post_code.h" #define DMP_CPUID_SX 0x31504d44 #define DMP_CPUID_DX 0x32504d44 @@ -35,11 +36,6 @@ #define DMP_CPUID_MX_PLUS 0x35504d44 #define DMP_CPUID_EX 0x37504d44 -/* Post codes */ -#define POST_DMP_ID_ERR 0x85 -#define POST_DRAM_TEST_ERR 0x86 -#define POST_DRAM_SIZING_ERR 0x77 - static u32 get_dmp_id(void) { return pci_read_config32(NB, NB_REG_CID); @@ -273,7 +269,7 @@ static void test_dram_stability(void) } } if (v != -1) { - post_code(POST_DRAM_TEST_ERR); + post_code(POST_DMP_DRAM_TEST_ERR); print_emerg("DRAM stablility test error!\nADDR = "); print_emerg_hex32(v); print_emerg(", WRITE = "); @@ -342,7 +338,7 @@ static void main(unsigned long bist) reg_nb_f1_cc &= ~(1 << 4); pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); if (detect_ddr3_dram_size()) { - post_code(POST_DRAM_SIZING_ERR); + post_code(POST_DMP_DRAM_SIZING_ERR); die("DRAM sizing error!\n"); } /* Reset enhance read push write to default(enable) */ diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..d16ee9a 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -28,6 +28,7 @@ #include "arch/io.h" #include "chip.h" #include "southbridge.h" +#include "mainboard/dmp/vortex86ex/dmp_post_code.h" /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ static const unsigned char irq_to_int_routing[16] = { @@ -89,12 +90,6 @@ static const unsigned char irq_to_int_routing[16] = { #define LPT_PDMAS 0 #define LPT_DREQS 0 -/* Post codes */ -#define POST_KBD_FW_UPLOAD 0x06 -#define POST_KBD_CHK_READY 0x07 -#define POST_KBD_IS_READY 0x08 -#define POST_KBD_FW_VERIFY_FAILURE 0x82 - static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -102,7 +97,7 @@ static u8 get_pci_dev_func(device_t dev) static void verify_dmp_keyboard_error(void) { - post_code(POST_KBD_FW_VERIFY_FAILURE); + post_code(POST_DMP_KBD_FW_VERIFY_ERR); die("Internal keyboard firmware verify error!\n"); } @@ -112,7 +107,7 @@ static void upload_dmp_keyboard_firmware(struct device *dev) u32 fwptr; // enable firmware uploading function by set bit 10. - post_code(POST_KBD_FW_UPLOAD); + post_code(POST_DMP_KBD_FW_UPLOAD); reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR); pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400); @@ -145,10 +140,10 @@ static void kbc_wait_system_flag(void) /* wait keyboard controller ready by checking system flag * (status port bit 2). */ - post_code(POST_KBD_CHK_READY); + post_code(POST_DMP_KBD_CHK_READY); while ((inb(0x64) & 0x4) == 0) { } - post_code(POST_KBD_IS_READY); + post_code(POST_DMP_KBD_IS_READY); } static void pci_routing_fixup(struct device *dev)

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coreboot-gerrit October 2013