Change in coreboot[master]: mb/google/volteer/var/voxel: disable DdiPortHpd

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46069 )

Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd
......................................................................

mb/google/volteer/var/voxel: disable DdiPortHpd

GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd

BUG=b:169690329
TEST=build and verify type-c(C0/C1) port functional normally

Signed-off-by: Pan Sheng-Liang 
Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e
---
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46069/1

diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 330d852..f3a04b4 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -1,4 +1,6 @@
 chip soc/intel/tigerlake
+	register "DdiPort1Hpd" = "0"
+	register "DdiPort2Hpd" = "0"
    register "tcc_offset" = "5"     # TCC of 95

register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46069 )

Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd
......................................................................

Patch Set 1: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46069 )

Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd
......................................................................

Patch Set 1: Code-Review+2

[TH Lin (Code Review)]

TH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46069 )

Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd
......................................................................

Patch Set 1: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46069 )

Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd
......................................................................

mb/google/volteer/var/voxel: disable DdiPortHpd

GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd

BUG=b:169690329
TEST=build and verify type-c(C0/C1) port functional normally

Signed-off-by: Pan Sheng-Liang 
Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: TH Lin 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sheng-Liang Pan: Looks good to me, but someone else must approve
  TH Lin: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 8ce6875..d7a265b 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -1,4 +1,6 @@
 chip soc/intel/tigerlake
+	register "DdiPort1Hpd" = "0"
+	register "DdiPort2Hpd" = "0"
    register "tcc_offset" = "5"     # TCC of 95

register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{