Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37167 )
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
src/arch/x86/car.ld: add AP entry address in CAR space
This is a placeholder for AP entry address for AMD platforms that support C environment bootblock. This shortcut address allows APs to jump to the AGESA entries directly after CAR setup and avoid looking for a scratch register for each family to store the AP entry address.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I177cd6f84c3f36776ec7bc8eeacb5b2a1d9142d2 --- M src/arch/x86/car.ld M src/arch/x86/include/arch/symbols.h 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37167/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 3680250..de760f8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,6 +68,11 @@ . += 80; _ecar_ehci_dbg_info = .;
+ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _car_amd_ap_entry = .; + . += 4; + _ecar_amd_ap_entry = .; + /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index efe10fe..9ab0dba 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -38,4 +38,6 @@ #define _car_ehci_dbg_info_size \ (_ecar_ehci_dbg_info - _car_ehci_dbg_info)
+extern unsigned long _car_amd_ap_entry; + #endif
Hello Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37167
to look at the new patch set (#2).
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
src/arch/x86/car.ld: add AP entry address in CAR space
This is a placeholder for AP entry address for AMD platforms that support C environment bootblock. This shortcut address allows APs to jump to the AGESA entries directly after CAR setup and avoid looking for a scratch register for each family to store the AP entry address.
TEST=boot PC Engines apu2 with C bootblock patch
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I177cd6f84c3f36776ec7bc8eeacb5b2a1d9142d2 --- M src/arch/x86/car.ld M src/arch/x86/include/arch/symbols.h 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37167/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37167 )
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
Patch Set 2:
At least fam14 has issues with cache coherency for CAR. You can try enabling CBMEM console for APs (SQUELCH_EARLY_SMP=n) and you will not get complete console log there. Depends of alignment AFAICS. But if we have an approach that avoids pushing AGESA quirks to common code, we should follow that path.
We should take suitable parts from amd/stoneyridge instead of making slighty modified copies, these should really merge into one AGESAv5 implementation eventually. Those PCI scratchpads were chosen because CAR shared across APs did not initially work there either and biosram_XX was not invented yet, either.
I think the correct thing to do would be to take biosram_XX implementation from amd/stoneyridge and implement both backup_top_of_low_cacheable() and ap_entry_ptr() on top of that. For all AGESA and binaryPI.
At the moment, urgent thing to do is have POSTCAR_STAGE=y in shape that can be merged, aka drop BINARYPI_LEGACY_WRAPPER entirely.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37167 )
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
Patch Set 2:
Patch Set 2:
At least fam14 has issues with cache coherency for CAR. You can try enabling CBMEM console for APs (SQUELCH_EARLY_SMP=n) and you will not get complete console log there. Depends of alignment AFAICS. But if we have an approach that avoids pushing AGESA quirks to common code, we should follow that path.
We should take suitable parts from amd/stoneyridge instead of making slighty modified copies, these should really merge into one AGESAv5 implementation eventually. Those PCI scratchpads were chosen because CAR shared across APs did not initially work there either and biosram_XX was not invented yet, either.
I think the correct thing to do would be to take biosram_XX implementation from amd/stoneyridge and implement both backup_top_of_low_cacheable() and ap_entry_ptr() on top of that. For all AGESA and binaryPI.
At the moment, urgent thing to do is have POSTCAR_STAGE=y in shape that can be merged, aka drop BINARYPI_LEGACY_WRAPPER entirely.
Good to know. The BIOS RAM area in ACPI MMIO looks very appropriate.
Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37167 )
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
Abandoned
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)