Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37167 )
Change subject: src/arch/x86/car.ld: add AP entry address in CAR space ......................................................................
Patch Set 2:
At least fam14 has issues with cache coherency for CAR. You can try enabling CBMEM console for APs (SQUELCH_EARLY_SMP=n) and you will not get complete console log there. Depends of alignment AFAICS. But if we have an approach that avoids pushing AGESA quirks to common code, we should follow that path.
We should take suitable parts from amd/stoneyridge instead of making slighty modified copies, these should really merge into one AGESAv5 implementation eventually. Those PCI scratchpads were chosen because CAR shared across APs did not initially work there either and biosram_XX was not invented yet, either.
I think the correct thing to do would be to take biosram_XX implementation from amd/stoneyridge and implement both backup_top_of_low_cacheable() and ap_entry_ptr() on top of that. For all AGESA and binaryPI.
At the moment, urgent thing to do is have POSTCAR_STAGE=y in shape that can be merged, aka drop BINARYPI_LEGACY_WRAPPER entirely.