Change in coreboot[master]: soc/intel/cannonlake: Set PCH Thermal Sensor configuration for S0ix

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Set PCH Thermal Sensor configuration for S0ix
......................................................................

soc/intel/cannonlake: Set PCH Thermal Sensor configuration for S0ix

Set PCH thermal sensor for dynamic thermal shutdown when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.

Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/cannonlake/finalize.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34522/1

diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 6083cab..eed042e 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -33,6 +33,7 @@
 #include <soc/smbus.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>
+#include <soc/intel/common/pch/include/thermal.h>

#include "chip.h"

@@ -62,6 +63,16 @@
    uint8_t reg8;

tco_lockdown();
+
+	/*
+	 * Set low maximum temp threshold value used for dynamic thermal sensor
+	 * shutdown consideration.
+	 *
+	 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+	 * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
+	 */
+	pch_thermal_configuration();
+
    /*
     * Disable ACPI PM timer based on dt policy
     *

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Set PCH Thermal Sensor configuration for S0ix
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34522/1/src/soc/intel/cannonlake/fi... 
File src/soc/intel/cannonlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/34522/1/src/soc/intel/cannonlake/fi... 
PS1, Line 36: #include <soc/intel/common/pch/include/thermal.h>
intelpch/thermal.h would be nit

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Set PCH Thermal Sensor configuration for S0ix
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34522/1/src/soc/intel/cannonlake/fi... 
File src/soc/intel/cannonlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/34522/1/src/soc/intel/cannonlake/fi... 
PS1, Line 36: #include <soc/intel/common/pch/include/thermal.h>
> intelpch/thermal. […]

Ack

Change in coreboot[master]: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

[Sumeet R Pawnikar (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34522

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
......................................................................

soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.

Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/finalize.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34522/2

Change in coreboot[master]: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

[Sumeet R Pawnikar (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34522

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
......................................................................

soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.

Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/finalize.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34522/4

Change in coreboot[master]: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34522 )

Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
......................................................................

soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.

Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522
Reviewed-by: Furquan Shaikh 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/finalize.c
2 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f859cd5..862b2e6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -97,6 +97,7 @@
    select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+	select SOC_INTEL_COMMON_BLOCK_THERMAL
    select SOC_INTEL_COMMON_PCH_BASE
    select SOC_INTEL_COMMON_NHLT
    select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 6083cab..c99653b 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -24,6 +24,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/tco.h>
+#include <intelblocks/thermal.h>
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <soc/p2sb.h>
@@ -62,6 +63,16 @@
    uint8_t reg8;

tco_lockdown();
+
+	/*
+	 * Set low maximum temp threshold value used for dynamic thermal sensor
+	 * shutdown consideration.
+	 *
+	 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+	 * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
+	 */
+	pch_thermal_configuration();
+
    /*
     * Disable ACPI PM timer based on dt policy
     *