Change in ...coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32252

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/1

diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc
index 7e74f09..ad9100f 100644
--- a/src/mainboard/intel/icelake_rvp/Makefile.inc
+++ b/src/mainboard/intel/icelake_rvp/Makefile.inc
@@ -29,6 +29,8 @@
 ramstage-y += mainboard.c
 ramstage-y += board_id.c

+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
 subdirs-y += variants/baseboard
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

diff --git a/src/mainboard/intel/icelake_rvp/smihandler.c b/src/mainboard/intel/icelake_rvp/smihandler.c
new file mode 100644
index 0000000..1ba7dee
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/smihandler.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/smm.h>
+#include <variant/ec.h>
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+
+void mainboard_smi_espi_handler(void)
+{
+	chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+			MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+			MAINBOARD_EC_SMI_EVENTS);
+	return 0;
+}
+
+#endif
\ No newline at end of file

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/32252/1/src/mainboard/intel/icelake_rvp/smih... 
File src/mainboard/intel/icelake_rvp/smihandler.c:

https://review.coreboot.org/#/c/32252/1/src/mainboard/intel/icelake_rvp/smih... 
PS1, Line 43: #endif
adding a line without newline at end of file

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32252

to look at the new patch set (#2).

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/2

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32252

to look at the new patch set (#3).

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/3

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 3:

(3 comments)

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG@7 
PS3, Line 7: mb/intel/icelake_rvp: Add SMI handlers
Is it Chrome EC specific?
> Add SMI handlers for Chrome EC

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG@11 
PS3, Line 11: 1. eSPI SMI event.
Please remove the dot at the end.

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG@15 
PS3, Line 15: Sleep(S3/S5)
Please add a space before (.

[Aamir Bohra (Code Review)]

Hello Subrata Banik, Wonkyu Kim, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32252

to look at the new patch set (#4).

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep (S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/4

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/32252/3//COMMIT_MSG@7 
PS3, Line 7: mb/intel/icelake_rvp: Add SMI handlers
> Is it Chrome EC specific? […]

Not really the, the CL adds strong functions for smm handlers defined under generic x86 smm handler module. However the calls inside those are chromeec specific, so until chrome ec configs are enabled, the APIs wouldn't be exposed.

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
File src/mainboard/intel/icelake_rvp/smihandler.c:

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
PS4, Line 4:  * Copyright (C) 2018 Intel Corporation.
2019

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
PS4, Line 23: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
CONFIG(

why does an intel board have an google chromeec?

[Aamir Bohra (Code Review)]

Hello Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32252

to look at the new patch set (#5).

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep (S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/5

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
File src/mainboard/intel/icelake_rvp/smihandler.c:

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
PS4, Line 4:  * Copyright (C) 2018 Intel Corporation.
> 2019

Done

https://review.coreboot.org/#/c/32252/4/src/mainboard/intel/icelake_rvp/smih... 
PS4, Line 23: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
> CONFIG( […]

It is interfaced via add in card. so with the AIC , the chromeec config needs to be selected.

Change in coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/32252/5/src/mainboard/intel/icelake... 
File src/mainboard/intel/icelake_rvp/smihandler.c:

https://review.coreboot.org/c/coreboot/+/32252/5/src/mainboard/intel/icelake... 
PS5, Line 23: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
do we really need to guard this ?

Change in coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32252 )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/32252/5/src/mainboard/intel/icelake... 
File src/mainboard/intel/icelake_rvp/smihandler.c:

https://review.coreboot.org/c/coreboot/+/32252/5/src/mainboard/intel/icelake... 
PS5, Line 23: #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
> do we really need to guard this ?

Yes, handlers inside uses chromeec APIs, had to guard.

[S] Change in coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32252?usp=email )

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.