Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47034/1
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca..6b47b8a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -467,8 +467,6 @@
RCBA32_OR(0x3434, 0x7); // LP LPC
- RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
pch_iobp_update(0xCF000000, ~0, 0x00007001); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ef7ebcf..167f4df 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -215,6 +215,7 @@ if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); }
reg32 = pci_read_config32(dev, 0x300);
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47034
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47034/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
Patch Set 3: Code-Review+1
tested?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
tested?
Not yet
Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47034
to look at the new patch set (#6).
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Tested on out-of-tree Compal LA-A992P, SATA still works.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47034/6
Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47034
to look at the new patch set (#9).
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Tested on out-of-tree Compal LA-A992P, SATA still works.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47034/9
Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
Patch Set 12: Code-Review+1
Attention is currently required from: Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
Patch Set 12: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47034 )
Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ......................................................................
sb/intel/lynxpoint: Relocate SATA clock gating write
Do it in the same place as Broadwell.
Tested on out-of-tree Compal LA-A992P, SATA still works.
Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47034 Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fc287b0..fb42145 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -565,8 +565,6 @@
RCBA32_OR(0x3434, 0x7); // LP LPC
- RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
pch_iobp_update(0xCF000000, ~0, 0x00007001); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 2a35600..1b69b80 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -187,6 +187,7 @@ if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); }
reg32 = pci_read_config32(dev, 0x300);