Change in coreboot[master]: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks"
Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44996
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Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks"
This reverts commit 1b89f5eeab3f28c6d4d096203c9bd0deaf21f19e.
Reason for revert: Breaks CFL. No agreement was reached on how to fix.
Change-Id: Ic39963d0f091a3c795b029b15dcd3d30bdd5cb8f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 9 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44996/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 753d8e0..bdbc323 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,40 +4,42 @@ help Intel Processor common GPIO support
-if SOC_INTEL_COMMON_BLOCK_GPIO - # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n - -endif diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 771c54c..6e8323f 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ help Intel Processor common SGX support
-if SOC_INTEL_COMMON_BLOCK_SGX - config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool + depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it.
config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" + depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -70,5 +70,3 @@ bool "Disabled"
endchoice - -endif diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index 3437ec7..7d30c41 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,10 +4,9 @@ help Intel Processor common UART support
-if SOC_INTEL_COMMON_BLOCK_UART - config INTEL_LPSS_UART_FOR_CONSOLE bool + depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -15,5 +14,3 @@ for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. - -endif
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1:
(1 comment)
Not necessary, sorry for the noise.
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG@11 PS1, Line 11: was `has been reached yet` I'd say
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG@11 PS1, Line 11: was
`has been reached yet` I'd say
But then it doesn't fit in 96 lines
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44996/1//COMMIT_MSG@11 PS1, Line 11: was
But then it doesn't fit in 96 lines
characters*
Looks like I forgot to have breakfast today...
Michael Niewöhner has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Removed Code-Review+2 by Michael Niewöhner foss@mniewoehner.de
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... File src/soc/intel/common/block/sgx/Kconfig:
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... PS1, Line 34: default 1 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB see below; drop this
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... PS1, Line 37: prompt "PRMRR size" this should depend on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... PS1, Line 38: if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE this is unneeded when dropping 1MB and disabled
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... PS1, Line 39: default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE see below; drop this
https://review.coreboot.org/c/coreboot/+/44996/1/src/soc/intel/common/block/... PS1, Line 64: config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB : depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB : bool "1 MiB" : : config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED : depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB : bool "Disabled" : since SGX depends on PRMRR >= 32 MiB, these two can be dropped
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44996 )
Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ......................................................................
Patch Set 1: Code-Review+1
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)