New subject: [L] Change in coreboot[master]: mb/asus/p2b: Add ACPI support for p3b-f

6 May 2020

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41098 )
Change subject: mb/asus/p2b: Add ACPI support for p3b-f
......................................................................
mb/asus/p2b: Add ACPI support for p3b-f
Finally!
Power button works to turn board on and off.
ACPI hooks to manipulate power and message LEDs work.
Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea
Signed-off-by: Keith Hui buurin@gmail.com
---
M src/mainboard/asus/p2b/Kconfig
M src/mainboard/asus/p2b/dsdt.asl
A src/mainboard/asus/p2b/suspend.asl
A src/mainboard/asus/p2b/variants/p3b-f/suspend.asl
4 files changed, 393 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41098/1

diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
index 1ad25e1..45018d6 100644
--- a/src/mainboard/asus/p2b/Kconfig
+++ b/src/mainboard/asus/p2b/Kconfig
@@ -29,7 +29,7 @@
    select HAVE_PIRQ_TABLE
    select BOARD_ROMSIZE_KB_256
    select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
-	select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS
+	select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
    select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS
config MAX_CPUS
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 88be9ba..623b575 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -53,6 +53,7 @@
    {
    	Offset (0x03),
    	TO12,   1, /* Device trap 12 */
+#if !CONFIG(BOARD_ASUS_P3B_F)
    	Offset (0x08),
    	FANM,   1, /* GPO0, meant for fan */
    	Offset (0x09),
@@ -61,33 +62,25 @@
    	    ,   2,
    	    ,   16,
    	MSG0,   1 /* GPO30, message LED */
+#endif
    }
-	/* Prepare To Sleep, Arg0 is target S-state */
-	Method (_PTS, 1, NotSerialized)
+	OperationRegion (ECOS, SystemIO, 0x72, 0x02)
+	Field (ECOS, ByteAcc, NoLock, Preserve)
    {
-		/* Disable fan, blink power LED, if not turning off */
-		If (LNotEqual (Arg0, 0x05))
-		{
-		    Store (Zero, FANM)
-		    Store (Zero, PLED)
-		}
-
-		/* Arms SMI for device 12 */
-		Store (One, TO12)
-		/* Put out a POST code */
-		Or (Arg0, 0xF0, P80)
+		CIDX,   8,
+		CDAT,   8
    }
-	Method (_WAK, 1, NotSerialized)
+	IndexField (CIDX, CDAT, ByteAcc, NoLock, Preserve)
    {
-		/* Re-enable fan, stop power led blinking */
-		Store (One, FANM)
-		Store (One, PLED)
-		/* wake OK */
-		Return(Package(0x02){0x00, 0x00})
+		Offset (0x58),
+		RTCS,   8,
+		Offset (0x5F),
+		SUS3,   1,
+		    ,   3,
+		SLST,   4
    }
-
    /* Root of the bus hierarchy */
    Scope (_SB)
    {
@@ -169,19 +162,9 @@
    	}
    }
-	/* ACPI Message */
-	Scope (_SI)
-	{
-		Method (_MSG, 1, NotSerialized)
-		{
-			If (LEqual (Arg0, Zero))
-			{
-				Store (One, MSG0)
-			}
-			Else
-			{
-				Store (Zero, MSG0)
-			}
-		}
-	}
+#if CONFIG(BOARD_ASUS_P3B_F)
+#include "variants/p3b-f/suspend.asl"
+#else
+#include "suspend.asl"
+#endif
 }
diff --git a/src/mainboard/asus/p2b/suspend.asl b/src/mainboard/asus/p2b/suspend.asl
new file mode 100644
index 0000000..5d2b540
--- /dev/null
+++ b/src/mainboard/asus/p2b/suspend.asl
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* ASUS P2B family board DSDT declarations (at top level) that does not apply to P3B-F */
+
+/**
+ * ACPI message indicator.
+ *
+ * @param Arg0 Number of waiting messages
+ */
+Scope (_SI)
+{
+	Method (_MSG, 1, NotSerialized)
+	{
+		If (LEqual (Arg0, Zero))
+		{
+			Store (One, MSG0)
+		}
+		Else
+		{
+			Store (Zero, MSG0)
+		}
+	}
+}
+
+/**
+ * Prepare To Sleep.
+ *
+ * @param Arg0 Target ACPI S-state
+ */
+Method (_PTS, 1, NotSerialized)
+{
+	/*SLST = Arg0*/
+	/* Disable fan, blink power LED. S5 will turn them off too */
+	If (Arg0 != 5)
+	{
+	    FANM = 0
+	    PLED = 0
+	}
+
+	/* Arms SMI for device 12 */
+	Store (One, TO12)
+	/* Put out a POST code */
+	P80 = 0xF0 | Arg0
+}
+
+/**
+ * System wake.
+ *
+ * Returns a 2-DWORD package of:
+ * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal))
+ * PSS: Actual S-state power supply entered if not 0
+ *
+ * @param Arg0 Target ACPI S-state
+ * @return See description
+ */
+Method (_WAK, 1, NotSerialized)
+{
+	/* Re-enable fan, stop power led blinking */
+	FANM = 1
+	PLED = 1
+	/* wake OK */
+	Return(Package(0x02){0x00, 0x00})
+}
+
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl
new file mode 100644
index 0000000..a84c700
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include "southbridge/intel/i82371eb/i82371eb.h"
+
+/* ASUS P3B-F board specific (top level) DSDT declarations */
+
+Name (PRW1, Package (0x04)
+{
+	Package (0x02) {0x09, 0x01},
+	Package (0x02) {0x08, 0x01},
+	Package (0x02) {0x0A, 0x01},
+	Package (0x02) {0x0B, 0x01}
+})
+
+Name (PRW3, Package (0x04)
+{
+	Package (0x02) { 0x09, 0x03 },
+	Package (0x02) { 0x08, 0x03 },
+	Package (0x02) { 0x0A, 0x03 },
+	Package (0x02) { 0x0B, 0x04 }
+})
+
+Name (PRWT, Package (0x04)
+{
+	0x09,
+	0x08,
+	0x0A,
+	0x0B
+})
+
+/* SPRW(n) = (SUS3==0) ? PRW1[n] : PRW3[n] */
+Method (SPRW, 1, NotSerialized)
+{
+	Store (Match (PRWT, MEQ, Arg0, MTR, 0x00, 0x00), Local0)
+	If (LEqual (SUS3, Zero))
+	{
+	    Return (DerefOf (Index (PRW1, Local0)))
+	}
+	Else
+	{
+	    Return (DerefOf (Index (PRW3, Local0)))
+	}
+}
+
+/*
+ * SMBus driver functions
+ *
+ * These functions communicate with the AS99127F ASIC on the P3B-F to handle hardware
+ * sequencing required around S3 suspend and resume. This chip is undocumented except it has
+ * W83781D-compatible hardware monitoring features, and seems to be responsible for hiding the
+ * flashchip from internal programming via flashrom.
+ *
+ * Note: The SMBus host controller interface is located in the southbridge.
+ */
+	/* The SMBus controller hardware interface. Only byte accesses covered. */
+	OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7)
+	Field (SM00, ByteAcc, NoLock, Preserve)
+	{
+		HSTS,   8,
+		Offset (0x02),
+		CTLR,   8,
+		CMDR,   8,
+		ADDR,   8,
+		DAT0,   8,
+		DAT1,   8
+	}
+	/* Wait for SMBus activity to complete, error or not */
+	Method (SWFS, 0, NotSerialized)
+	{
+		And (HSTS, 0x06, Local0)
+		While (Local0 == 0)
+		{
+			Stall (1)
+			And (HSTS, 0x06, Local0)
+		}
+	}
+
+	/**
+	* Writes a byte to a SMBus device.
+	*
+	* @param Arg0 SMBus device ID << 1
+	* @param Arg1 Command (register index in our case)
+	* @param Arg2 Data
+	*/
+	Method (WBYT, 3, NotSerialized)
+	{
+		Store (Arg0, ADDR)
+		Store (Arg1, CMDR)
+		Store (Arg2, DAT0)
+		Store (0xFF, HSTS)
+		Store (0x48, CTLR) /* Start a byte data R/W access */
+		SWFS ()
+	}
+
+	/**
+	* Reads a byte from a SMBus device.
+	*
+	* @param Arg0 SMBus device ID << 1
+	* @param Arg1 Command (register index in our case)
+	* @return Data read
+	*/
+	Method (RBYT, 2, NotSerialized)
+	{
+		Or (Arg0, 0x01, ADDR) /* Set bit 0, this will be a read */
+		Store (Arg1, CMDR)
+		Store (0xFF, HSTS)
+		Store (0x48, CTLR) /* Start a byte data R/W access */
+
+		/* If interrupted without success, restart and try again */
+		And (HSTS, 0x02, Local0)
+		While (LEqual (Local0, Zero))
+		{
+			Store (0xFF, HSTS)
+			Store (0x48, CTLR)
+			SWFS ()
+			And (HSTS, 0x02, Local0)
+		}
+
+		Return (DAT0) /* \DAT0 */
+	}
+
+	Method (SGOH, 2, NotSerialized)
+	{
+		/* SMBus address 0x48 */
+		Store (0x90, Local0)
+		Store (RBYT (Local0, Arg0), Local1)
+		Or (Local1, Arg1, Local1)
+		WBYT (Local0, Arg0, Local1)
+	}
+
+	Method (SGOL, 2, NotSerialized)
+	{
+		Store (0x90, Local0)
+		Store (RBYT (Local0, Arg0), Local1)
+		Not (Arg1, Local2)
+		And (Local1, Local2, Local1)
+		WBYT (Local0, Arg0, Local1)
+	}
+
+	Method (FANC, 1, NotSerialized)
+	{
+		/* SMBus address 0x2d */
+		WBYT (0x5A, 0x59, Arg0)
+	}
+
+	Method (FANP, 1, NotSerialized)
+	{
+		WBYT (0x5A, 0x5A, Arg0)
+	}
+
+	Method (EN18, 0, NotSerialized)
+	{
+		Store (0x5A, Local0)
+		Store (RBYT (Local0, 0x5F), Local1)
+		And (Local1, 0xDF, Local1)
+		WBYT (Local0, 0x5F, Local1)
+	}
+
+	Method (DS18, 0, NotSerialized)
+	{
+		Store (0x5A, Local0)
+		Store (RBYT (Local0, 0x5F), Local1)
+		Or (Local1, 0x20, Local1)
+		WBYT (Local0, 0x5F, Local1)
+	}
+
+/**
+ * Prepare To Sleep,
+ *
+ * @param Arg0 Target ACPI S-state
+ */
+    Method (_PTS, 1, NotSerialized)
+    {
+        SLST = Arg0
+        If (Arg0 == 0x01)
+        {
+	/* Disable BX.PMCR[CRst_En] */
+            Store (_SB.PCI0.NB.PMCR, Local0)
+            And (Local0, 0xFE, _SB.PCI0.NB.PMCR)
+
+	/* Isolate CPU_STP# and SUS_STAT1# signals at GENCFG register */
+            Store (_SB.PCI0.PX40.FXS1, Local0)
+            Or (Local0, 0x24, Local1)
+            Store (Local1, _SB.PCI0.PX40.FXS1)
+
+            _SB.PCI0.ENTER_CONFIG_MODE (0x0A)
+	    /* In SIO Dev A CR E4 = xxxx01xx (these bits are reserved per datasheet?) */
+            And (_SB.PCI0.KBWK, 0xF7, Local0)
+            Or (Local0, 0x04, _SB.PCI0.KBWK)
+            _SB.PCI0.EXIT_CONFIG_MODE ()
+        }
+
+        If (Arg0 == 0x03)
+        {
+            SGOH (0x83, 0x04)
+            SGOL (0x80, 0x04)
+            SGOH (0x80, 0x04)
+            SGOH (0x83, 0x01)
+            EN18 ()
+        }
+
+	/* Arms SMI for device 12 */
+	TO12 = 1
+	/* Put out a POST code */
+	P80 = 0xF0 | Arg0
+    }
+
+/**
+ * System wake.
+ *
+ * Returns a 2-DWORD package of:
+ * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal))
+ * PSS: Actual S-state power supply entered if not 0
+ *
+ * @param Arg0 Target ACPI S-state
+ * @return See description
+ */
+    Method (_WAK, 1, NotSerialized)  // _WAK: Wake
+    {
+        DS18 ()
+        Store (Zero, TO12)
+	/* Restore CPU_STP# and SUS_STAT1# signals */
+        Store (_SB.PCI0.PX40.FXS1, Local0)
+        And (Local0, 0xDB, _SB.PCI0.PX40.FXS1)
+        SGOL (0x83, 0x01)
+        _SB.PCI0.ENTER_CONFIG_MODE (0x0A)
+        And (_SB.PCI0.MSWK, 0xFD, Local1)
+        Store (Local1, _SB.PCI0.MSWK)
+	/* In SIO Dev A CR E4 = xxxx00xx */
+        And (_SB.PCI0.KBWK, 0xF3, Local0)
+        Store (Local0, _SB.PCI0.KBWK)
+        _SB.PCI0.EXIT_CONFIG_MODE ()
+	/* Put out a POST code */
+	P80 = 0xFF
+ 	Return(Package(0x02){0x00, 0x00})
+   }
+
+    Scope (_GPE)
+    {
+        Method (_L0A, 0, NotSerialized)  // _Lxx: Level-Triggered GPE
+        {
+            Notify (_SB.PCI0.SER2, 0x02) // Device Wake
+            Notify (_SB.PCI0.SER3, 0x02) // Device Wake
+        }
+
+        Method (_L09, 0, NotSerialized)  // _Lxx: Level-Triggered GPE
+        {
+            Notify (_SB.PCI0, 0x02) // Device Wake
+        }
+    }
+
+Scope (_SI)
+{
+	/**
+	 * ACPI message indicator
+	 *
+	 * @param Arg0 Number of waiting messages
+	 */
+        Method (_MSG, 1, NotSerialized)
+        {
+            If (LEqual (Arg0, Zero))
+            {
+                SGOL (0x81, 0x02)
+                SGOH (0x81, 0x01)
+                SGOL (0x81, 0x01)
+            }
+            Else
+            {
+                SGOH (0x81, 0x02)
+                SGOL (0x81, 0x02)
+            }
+        }
+
+
+	/**
+	 * System Status. OS calls to set system status indicator.
+	 * Arg0:
+	 * 0 = Indicator off
+	 * 1 = Working
+	 * 2 = Waking
+	 * 3 = Sleeping: States S1, S2, S3
+	 * 4 = Sleeping with context saved to non-volatile storage.
+	 *
+	 * @param Arg0 System status indicator
+	 */
+	Method (_SST, 1, NotSerialized)  // _SST: System Status
+	{
+		If (LEqual (Arg0, 0x00))
+		{
+			SGOH (0x80, 0x40)
+		}
+		ElseIf (LEqual (Arg0, 0x03))
+		{
+			SGOL (0x80, 0x40)
+			SGOL (0x80, 0x80)
+			FANC (0x81)
+			FANP (0x81)
+		}
+		Else
+		{
+			SGOL (0x80, 0x40)
+			SGOH (0x80, 0x80)
+			FANC (0x8F)
+			FANP (0x8F)
+		}
+	}
+}
+
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea
Gerrit-Change-Number: 41098
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui buurin@gmail.com
Gerrit-MessageType: newchange



    