Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58707 )

Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
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soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA

AMD platforms require the destination buffer to be 64 byte aligned
when using the SPI DMA controller.

BUG=b:179699789
TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug
$1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0}

Signed-off-by: Raul E Rangel 
Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Julius Werner 
---
M src/soc/amd/common/block/lpc/Kconfig
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index e775606..76f4ec7 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -16,6 +16,12 @@
    help
      Select this option to enable SPI DMA support.

+# The LPC SPI DMA controller requires the destination buffers to be 64 byte
+# aligned.
+config CBFS_CACHE_ALIGN
+	int
+	default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+
 config SOC_AMD_COMMON_BLOCK_HAS_ESPI
    bool
    help

7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.