Change in coreboot[master]: sb/intel/i82801jx: Drop `c3_latency`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42656 )

Change subject: sb/intel/i82801jx: Drop `c3_latency`
......................................................................

sb/intel/i82801jx: Drop `c3_latency`

The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/i82801jx/chip.h
M src/southbridge/intel/i82801jx/fadt.c
2 files changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42656/1

diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index 028d5c8..ba8d007 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -48,7 +48,6 @@
    int c4onc3_enable:1;
    int c5_enable : 1;
    int c6_enable : 1;
-	int c3_latency;
    int docking_supported:1;

int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 9d86b19..7925477 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -42,7 +42,7 @@
    fadt->gpe1_blk_len = 0;
    fadt->gpe1_base = 0;
    fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = chip->c3_latency;
+	fadt->p_lvl3_lat = 0;	/* FIXME: Is this correct? */
    fadt->flush_size = 0;
    fadt->flush_stride = 0;
    fadt->duty_offset = 1;

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42656

to look at the new patch set (#5).

Change subject: sb/intel/i82801jx: Drop `c3_latency`
......................................................................

sb/intel/i82801jx: Drop `c3_latency`

The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/i82801jx/chip.h
M src/southbridge/intel/i82801jx/fadt.c
2 files changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42656/5

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42656 )

Change subject: sb/intel/i82801jx: Drop `c3_latency`
......................................................................

Patch Set 5: Code-Review+1

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42656 )

Change subject: sb/intel/i82801jx: Drop `c3_latency`
......................................................................

Patch Set 5: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42656 )

Change subject: sb/intel/i82801jx: Drop `c3_latency`
......................................................................

sb/intel/i82801jx: Drop `c3_latency`

The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Nico Huber 
---
M src/southbridge/intel/i82801jx/chip.h
M src/southbridge/intel/i82801jx/fadt.c
2 files changed, 1 insertion(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  HAOUAS Elyes: Looks good to me, but someone else must approve

diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index 028d5c8..ba8d007 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -48,7 +48,6 @@
    int c4onc3_enable:1;
    int c5_enable : 1;
    int c6_enable : 1;
-	int c3_latency;
    int docking_supported:1;

int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index f2b408b..d99872d 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -36,7 +36,7 @@
    fadt->pm_tmr_len = 4;
    fadt->gpe0_blk_len = 16;
    fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = chip->c3_latency;
+	fadt->p_lvl3_lat = 0;	/* FIXME: Is this correct? */
    fadt->duty_offset = 1;
    fadt->duty_width = 0;
    fadt->day_alrm = 0xd;