Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42657 )
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
sb/intel/i82801jx: Drop `docking_supported`
The three mainboards using this southbridge are desktop boards, which are not dockable. The Dell Precision M6400 laptop is dockable, but even though it has an Eaglelake MCH, it uses an i82801ix southbridge instead. So, one could still port that laptop to coreboot after this change! :P
Also, drop the now-unnecessary `chip` and `dev` variables.
Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/fadt.c 2 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42657/1
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ba8d007..cdc1cc5 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -48,7 +48,6 @@ int c4onc3_enable:1; int c5_enable : 1; int c6_enable : 1; - int docking_supported:1;
int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 7925477..f48f65b 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -6,13 +6,10 @@ #include <cpu/x86/smm.h> #include <version.h> #include <southbridge/intel/common/pmutil.h> -#include "chip.h"
void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(0x1f, 0); - struct southbridge_intel_i82801jx_config *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9;
@@ -55,8 +52,6 @@ | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER | ACPI_FADT_C2_MP_SUPPORTED); - if (chip->docking_supported) - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8;
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42657 )
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
Patch Set 4: Code-Review+1
Hello build bot (Jenkins), Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42657
to look at the new patch set (#5).
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
sb/intel/i82801jx: Drop `docking_supported`
The three mainboards using this southbridge are desktop boards, which are not dockable. The Dell Precision M6400 laptop is dockable, but even though it has an Eaglelake MCH, it uses an i82801ix southbridge instead. So, one could still port that laptop to coreboot after this change! :P
Also, drop the now-unnecessary `chip` and `dev` variables.
Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/fadt.c 2 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42657/5
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42657 )
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
Patch Set 5: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42657 )
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42657 )
Change subject: sb/intel/i82801jx: Drop `docking_supported` ......................................................................
sb/intel/i82801jx: Drop `docking_supported`
The three mainboards using this southbridge are desktop boards, which are not dockable. The Dell Precision M6400 laptop is dockable, but even though it has an Eaglelake MCH, it uses an i82801ix southbridge instead. So, one could still port that laptop to coreboot after this change! :P
Also, drop the now-unnecessary `chip` and `dev` variables.
Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42657 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/fadt.c 2 files changed, 1 insertion(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ba8d007..cdc1cc5 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -48,7 +48,6 @@ int c4onc3_enable:1; int c5_enable : 1; int c6_enable : 1; - int docking_supported:1;
int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index d99872d..fd55661 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -5,13 +5,10 @@ #include <cpu/x86/smm.h> #include <version.h> #include <southbridge/intel/common/pmutil.h> -#include "chip.h"
void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(0x1f, 0); - struct southbridge_intel_i82801jx_config *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9;
@@ -46,8 +43,6 @@ fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_C2_MP_SUPPORTED); - if (chip->docking_supported) - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32;
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)