Angel Pons submitted this change.
sb/intel/i82801jx: Drop `c3_latency`
The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.
Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
M src/southbridge/intel/i82801jx/chip.h
M src/southbridge/intel/i82801jx/fadt.c
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index 028d5c8..ba8d007 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -48,7 +48,6 @@
int c4onc3_enable:1;
int c5_enable : 1;
int c6_enable : 1;
- int c3_latency;
int docking_supported:1;
int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index f2b408b..d99872d 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -36,7 +36,7 @@
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = chip->c3_latency;
+ fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
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