Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15861
-gerrit
commit 38de68812fc841bdb51df361260d5db5dc49a1b9 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon Jul 25 07:11:05 2016 -0700
soc/intel/quark: Initialize MTRRs in bootblock
Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs.
TEST=Build and run on Galileo Gen2.
Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/bootblock/bootblock.c | 25 +++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 1 + src/soc/intel/quark/reg_access.c | 1 - 3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 4aa774b..e8fecc2 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> +#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h>
@@ -47,8 +48,26 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END };
+static const struct reg_script mtrr_init[] = { + /* Cache the SPI flash */ + REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_TYPE_WRBACK)), + REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_PHYS_MASK_VALID)), + + /* Cache ESRAM */ + REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000 + | MTRR_TYPE_WRBACK)), + REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff) + | MTRR_PHYS_MASK_VALID)), + REG_SCRIPT_END +}; + void bootblock_soc_early_init(void) { + /* Initialize the MTRRs */ + reg_script_run(mtrr_init); + /* Initialize the controllers */ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); @@ -60,6 +79,12 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); }
+void bootblock_soc_init(void) +{ + /* Display the MTRRs */ + soc_display_mtrrs(); +} + void platform_prog_run(struct prog *prog) { /* Display the program entry point */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index a07bd22..0e64917 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -20,6 +20,7 @@
#include <arch/io.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 7383ddd..621ef74 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,7 +15,6 @@
#define __SIMPLE_DEVICE__
-#include <cpu/x86/mtrr.h> #include <console/console.h> #include <soc/pci_devs.h> #include <soc/ramstage.h>
-
Lee Leahy