Change in coreboot[master]: soc/intel/alderlake: Fix for PCIe source clock assignment

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Cliff Huang, Jeremy Compostella, Tim Wawrzynczak.
Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Eric Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63947

to look at the new patch set (#7).

Change subject: soc/intel/alderlake: Fix for PCIe source clock assignment
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soc/intel/alderlake: Fix for PCIe source clock assignment

When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang 
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63947/7