Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in ...

[Anil Kumar K (Code Review)]

Attention is currently required from: Patrick Rudolph.
Anil Kumar K has uploaded a new patch set (#2) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/55240 )

Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards
......................................................................

vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes
in FSP v2127_00 onwards

With XMP3.0 support added for DDR5 in ADL, the MEMORY_INFO_DATA_HOB
structure changed and these changes need to be aligned in vendorcode.
To align the structres we update the MemInfoHob header file in vendorcode

Bug=None
Branch=None
Test=build coreboot and boot on ADLRVP . Confirm the mosys command displays memory info correctly
$mosys memory spd print all

Signed-off-by: Anil Kumar 
Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
1 file changed, 31 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/55240/2