Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39441 )
Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ......................................................................
soc/intel/tigerlake: Enable HDA through dev_enabled
Check for dev enabled status for HDA controller and update the UPD accordingly.
BUG=151174264 BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/39441/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index f0f3b4c..4b9b007 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -28,6 +28,7 @@ { unsigned int i; uint32_t mask = 0; + const struct device *dev;
/* Set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = 0xFE; @@ -70,7 +71,7 @@ * Skip IGD initialization in FSP if device * is disable in devicetree.cb. */ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) m_cfg->InternalGfx = 0; else @@ -113,6 +114,12 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39441 )
Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ......................................................................
Patch Set 1: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39441 )
Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ......................................................................
Patch Set 1: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39441 )
Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39441 )
Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ......................................................................
soc/intel/tigerlake: Enable HDA through dev_enabled
Check for dev enabled status for HDA controller and update the UPD accordingly.
BUG=151174264 BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 8 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index f0f3b4c..4b9b007 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -28,6 +28,7 @@ { unsigned int i; uint32_t mask = 0; + const struct device *dev;
/* Set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = 0xFE; @@ -70,7 +71,7 @@ * Skip IGD initialization in FSP if device * is disable in devicetree.cb. */ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) m_cfg->InternalGfx = 0; else @@ -113,6 +114,12 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
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Caveh Jalali (Code Review) -
Patrick Georgi (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)