CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
soc/mediatek/mt8192: Initial commit
Add MT8192 address map, memlayout and first Kconfig.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43957/1
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig new file mode 100644 index 0000000..2412204 --- /dev/null +++ b/src/soc/mediatek/mt8192/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8192 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8192 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h new file mode 100755 index 0000000..c4b3047 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, + UART0_BASE = IO_PHYS + 0x01002000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, + SFLASH_REG_BASE = IO_PHYS + 0x01234000, + IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + IOCFG_BM_BASE = IO_PHYS + 0x01D10000, + IOCFG_BL_BASE = IO_PHYS + 0x01D30000, + IOCFG_BR_BASE = IO_PHYS + 0x01D40000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + IOCFG_LB_BASE = IO_PHYS + 0x01E70000, + IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, + IOCFG_LT_BASE = IO_PHYS + 0x01F20000, + IOCFG_TL_BASE = IO_PHYS + 0x01F30000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + MSDC0_BASE = IO_PHYS + 0x01F60000, +}; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld new file mode 100644 index 0000000..df9d376 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) + SRAM_END(0x00120000) + + SRAM_L2C_START(0x00200000) + BOOTBLOCK(0x00201000, 64K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40000000, 2M) + RAMSTAGE(0x40200000, 256K) + + BL31(0x54600000, 0x60000) +}
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
@CK please add yupingso for all changes here.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
From lint error: "File src/soc/mediatek/mt8192/include/soc/addressmap.h has one or more executable bits set in the file permissions."
Please chmod -x addressmap.h and then re-submit.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit Please make it a statement by adding a verb (in imperative mood). Maybe:
soc/mediatek/mt8192: Add new ARMv8 device MT8192
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@10 PS1, Line 10: Please give more details about the device. Is it similar to an already support device?
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
Please make it a statement by adding a verb (in imperative mood). Maybe: […]
I would like it to be: 'soc/mediatek/mt8192: Add address map, memlayout and Kconfig for MT8192 SoC' because this patch does not have any executable code in it.
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@10 PS1, Line 10:
Please give more details about the device. […]
OK, this is similar to MT8183 and I would add more details.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
I would like it to be: 'soc/mediatek/mt8192: Add address map, memlayout and Kconfig for MT8192 SoC' […]
that sounds too detailed. what about
soc/media/mt8192: Add initial config for new ARMv8 device MT8192
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
that sounds too detailed. what about […]
Sounds good to me.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Initial commit ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
Sounds good to me.
Any update?
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43957
to look at the new patch set (#2).
Change subject: soc/media/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
soc/media/mt8192: Add initial config for new ARMv8 device MT8192
Add MT8192 address map, memlayout and first Kconfig.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43957/2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/media/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
Any update?
Ack
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@10 PS1, Line 10:
OK, this is similar to MT8183 and I would add more details.
no details yet?
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43957
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192
Add MT8192 address map, memlayout and first Kconfig.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43957/3
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43957
to look at the new patch set (#4).
Change subject: soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192
Add MT8192 address map, memlayout and first Kconfig. MT8192 is similar to MT8183.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43957/4
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@7 PS1, Line 7: soc/mediatek/mt8192: Initial commit
Ack
Done
https://review.coreboot.org/c/coreboot/+/43957/1//COMMIT_MSG@10 PS1, Line 10:
no details yet?
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
Patch Set 4: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43957 )
Change subject: soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192 ......................................................................
soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192
Add MT8192 address map, memlayout and first Kconfig. MT8192 is similar to MT8183.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43957 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig new file mode 100644 index 0000000..2412204 --- /dev/null +++ b/src/soc/mediatek/mt8192/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8192 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8192 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h new file mode 100644 index 0000000..c4b3047 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, + UART0_BASE = IO_PHYS + 0x01002000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, + SFLASH_REG_BASE = IO_PHYS + 0x01234000, + IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + IOCFG_BM_BASE = IO_PHYS + 0x01D10000, + IOCFG_BL_BASE = IO_PHYS + 0x01D30000, + IOCFG_BR_BASE = IO_PHYS + 0x01D40000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + IOCFG_LB_BASE = IO_PHYS + 0x01E70000, + IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, + IOCFG_LT_BASE = IO_PHYS + 0x01F20000, + IOCFG_TL_BASE = IO_PHYS + 0x01F30000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + MSDC0_BASE = IO_PHYS + 0x01F60000, +}; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld new file mode 100644 index 0000000..df9d376 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) + SRAM_END(0x00120000) + + SRAM_L2C_START(0x00200000) + BOOTBLOCK(0x00201000, 64K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40000000, 2M) + RAMSTAGE(0x40200000, 256K) + + BL31(0x54600000, 0x60000) +}
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CK HU (Code Review) -
Hung-Te Lin (Code Review)
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Paul Menzel (Code Review)
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Yu-Ping Wu (Code Review)