Change in coreboot[master]: [WIP]soc/intel/xeon_sp: Allow experimental long mode support
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48502 )
Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ......................................................................
[WIP]soc/intel/xeon_sp: Allow experimental long mode support
The acpi_create_rmrr code needs to be cleaned up.
Change-Id: I96817f69cdcaa1ea040bc328c50f5ab23c637cb2 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/nb_acpi.c 3 files changed, 20 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48502/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..8d9e469 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -25,7 +25,8 @@
config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4fe8b20..807083f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -219,9 +219,9 @@ // apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + printk(BIOS_SPEW, "%s injecting NVSA with 0x%lx\n", __FILE__, (uintptr_t)gnvs); acpigen_write_scope("\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_write_name_dword("NVSA", (uint32_t)(uintptr_t)gnvs); acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 19c3921..f586d9b 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -292,11 +292,11 @@
for (int stack = 0; stack <= PSTACK2; ++stack) { uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + uintptr_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%lx, " "vtd_mmio_cap: 0x%llx\n", __func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
@@ -322,24 +322,24 @@
static unsigned long acpi_create_rmrr(unsigned long current) { - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); +// uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000);
- uint32_t *ptr; + /* uint32_t *ptr; */
- // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } + /* // reserve memory */ + /* ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); */ + /* if (!ptr) { */ + /* ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); */ + /* assert(ptr != NULL); */ + /* memset(ptr, 0, size); */ + /* } */
unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); + /* printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " */ + /* "End Address (limit): 0x%x\n", */ + /* 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); */ + /* current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, */ + /* (uint32_t) ((uint32_t) ptr + size - 1)); */
printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n",
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48502 )
Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 332: /* ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 333: /* assert(ptr != NULL); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 334: /* memset(ptr, 0, size); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 338: /* printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 339: /* "End Address (limit): 0x%x\n", */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 340: /* 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 342: /* (uint32_t) ((uint32_t) ptr + size - 1)); */ please, no space before tabs
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48502?usp=email )
Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ......................................................................
Abandoned
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Arthur Heymans (Code Review) -
build bot (Jenkins) (Code Review)
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Stefan Reinauer (Code Review)