Change in coreboot[master]: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41852 )

Change subject: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler
......................................................................

sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler

The xHCI S3/S4 quirk is only needed on PPT Revision A0.
Fix always false condition by adding the missing read32 function call.

Untested.

Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/smihandler.c
1 file changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41852/1

diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index cddb4cf..fbc7b81 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -100,6 +100,9 @@
    switch (slp_typ) {
    case ACPI_S3:
    case ACPI_S4:
+		if (!pch_silicon_supported(PCH_TYPE_PPT, PCH_STEP_A0))
+			break;
+
    	reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
    	reg16 &= ~0x03UL;
    	pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
@@ -112,14 +115,13 @@
    			              PCI_BASE_ADDRESS_0) & ~0xFUL;

if (!smm_validate_pointer((void *)(uintptr_t)xhci_bar)) {
-			/* FIXME: This looks broken */
-			if ((xhci_bar + 0x4C0) & 1)
+			if (read32(xhci_bar + 0x4C0) & 1)
    			pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
-			if ((xhci_bar + 0x4D0) & 1)
+			if (read32(xhci_bar + 0x4D0) & 1)
    			pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
-			if ((xhci_bar + 0x4E0) & 1)
+			if (read32(xhci_bar + 0x4E0) & 1)
    			pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
-			if ((xhci_bar + 0x4F0) & 1)
+			if (read32(xhci_bar + 0x4F0) & 1)
    			pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
    	}
    	reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);