New subject: Change in coreboot[master]: nb/intel/common: Introduce common MCHBAR accessor functions

18 Sep 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45517 )
Change subject: nb/intel/pineview: Use new mchbar{8,16,32}_and_or()
......................................................................
nb/intel/pineview: Use new mchbar{8,16,32}_and_or()
Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
A src/northbridge/intel/common/mchbar_ops.c
A src/northbridge/intel/common/mchbar_ops.h
M src/northbridge/intel/pineview/Makefile.inc
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/pineview.h
M src/northbridge/intel/pineview/raminit.c
6 files changed, 417 insertions(+), 344 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45517/1

diff --git a/src/northbridge/intel/common/mchbar_ops.c b/src/northbridge/intel/common/mchbar_ops.c
new file mode 100644
index 0000000..c3fccad
--- /dev/null
+++ b/src/northbridge/intel/common/mchbar_ops.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <stdint.h>
+#include "mchbar_ops.h"
+
+void mchbar8_and_or(int offset, u8 mask, u8 or)
+{
+	u8 reg8 = MCHBAR8(offset);
+
+	reg8 &= mask;
+	reg8 |= or;
+	MCHBAR8(offset) = reg8;
+}
+
+void mchbar16_and_or(int offset, u16 mask, u16 or)
+{
+	u16 reg16 = MCHBAR32(offset);
+
+	reg16 &= mask;
+	reg16 |= or;
+	MCHBAR16(offset) = reg16;
+}
+
+void mchbar32_and_or(int offset, u32 mask, u32 or)
+{
+	u32 reg32 = MCHBAR32(offset);
+
+	reg32 &= mask;
+	reg32 |= or;
+	MCHBAR32(offset) = reg32;
+}
+
+void mchbar8_and(int offset, u8 and)
+{
+	mchbar8_and_or(offset, and, 0);
+}
+
+void mchbar16_and(int offset, u16 and)
+{
+	mchbar16_and_or(offset, and, 0);
+}
+
+void mchbar32_and(int offset, u32 and)
+{
+	mchbar32_and_or(offset, and, 0);
+}
+
+void mchbar8_or(int offset, u8 or)
+{
+	mchbar8_and_or(offset, 0xff, or);
+}
+
+void mchbar16_or(int offset, u16 or)
+{
+	mchbar16_and_or(offset, 0xffff, or);
+}
+
+void mchbar32_or(int offset, u32 or)
+{
+	mchbar32_and_or(offset, 0xffffffff, or);
+}
diff --git a/src/northbridge/intel/common/mchbar_ops.h b/src/northbridge/intel/common/mchbar_ops.h
new file mode 100644
index 0000000..cf39c2b
--- /dev/null
+++ b/src/northbridge/intel/common/mchbar_ops.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MCHBAR_OPS_H
+#define MCHBAR_OPS_H
+
+#include <stdint.h>
+#include <northbridge/intel/pineview/memmap.h>
+
+#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x)))
+#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x)))
+#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x)))
+
+void mchbar8_and_or(int offset, u8 mask, u8 or);
+void mchbar16_and_or(int offset, u16 mask, u16 or);
+void mchbar32_and_or(int offset, u32 mask, u32 or);
+void mchbar8_and(int offset, u8 and);
+void mchbar16_and(int offset, u16 and);
+void mchbar32_and(int offset, u32 and);
+void mchbar8_or(int offset, u8 or);
+void mchbar16_or(int offset, u16 or);
+void mchbar32_or(int offset, u32 or);
+
+#endif
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index 08e04f2..4ba902e 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -14,6 +14,7 @@
 romstage-y += memmap.c
 romstage-y += raminit.c
 romstage-y += early_init.c
+romstage-y +=  ../common/mchbar_ops.c
postcar-y += memmap.c
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 42a68d8..ec7c575 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <northbridge/intel/common/mchbar_ops.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <northbridge/intel/pineview/chip.h>
 #include <option.h>
@@ -67,10 +68,10 @@
if (config->use_crt) {
    	/* Enable VGA */
-		MCHBAR32_OR(DACGIOCTRL1, 1 << 15);
+		mchbar32_or(DACGIOCTRL1, 1 << 15);
    } else {
    	/* Disable VGA */
-		MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15));
+		mchbar32_and(DACGIOCTRL1, ~(1 << 15));
    }
if (config->use_lvds) {
@@ -79,17 +80,17 @@
    	reg32 &= ~0xf1000000;
    	reg32 |=  0x90000000;
    	MCHBAR32(LVDSICR2) = reg32;
-		MCHBAR32_OR(IOCKTRR1, 1 << 9);
+		mchbar32_or(IOCKTRR1, 1 << 9);
    } else {
    	/* Disable LVDS */
-		MCHBAR32_OR(DACGIOCTRL1, 3 << 25);
+		mchbar32_or(DACGIOCTRL1, 3 << 25);
    }
MCHBAR32(CICTRL) = 0xc6db8b5f;
    MCHBAR16(CISDCTRL) = 0x024f;
-	MCHBAR32_AND(DACGIOCTRL1, 0xffffff00);
-	MCHBAR32_OR(DACGIOCTRL1,  1 << 5);
+	mchbar32_and(DACGIOCTRL1, 0xffffff00);
+	mchbar32_or(DACGIOCTRL1,  1 << 5);
/* Legacy backlight control */
    pci_write_config8(GMCH_IGD, 0xf4, 0x4c);
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 03fa318..121c65b 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -5,6 +5,7 @@
#include <northbridge/intel/pineview/memmap.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#include <northbridge/intel/common/mchbar_ops.h>
#define BOOT_PATH_NORMAL	0
 #define BOOT_PATH_RESET		1
@@ -36,23 +37,8 @@
/*
  * MCHBAR
+ *As there are many registers, define them on a separate file
  */
-
-#define MCHBAR8(x)  (*((volatile u8  *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR +  x)))	/* FIXME: causes changes */
-#define MCHBAR8_AND(x,  and) (MCHBAR8(x)  = MCHBAR8(x)  & (and))
-#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
-#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
-#define MCHBAR8_OR(x,   or)  (MCHBAR8(x)  = MCHBAR8(x)  | (or))
-#define MCHBAR16_OR(x,  or)  (MCHBAR16(x) = MCHBAR16(x) | (or))
-#define MCHBAR32_OR(x,  or)  (MCHBAR32(x) = MCHBAR32(x) | (or))
-#define MCHBAR8_AND_OR(x,  and, or) (MCHBAR8(x)  = (MCHBAR8(x)  & (and)) | (or))
-#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
-#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
-
-/* As there are many registers, define them on a separate file */
-
 #include "mchbar_regs.h"
/*
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 43149be..b190781 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <delay.h>
 #include <lib.h>
+#include <northbridge/intel/common/mchbar_ops.h>
 #include "pineview.h"
 #include "raminit.h"
 #include <spd.h>
@@ -501,7 +502,7 @@
    if (s->boot_path == BOOT_PATH_RESET)
    	return;
-	MCHBAR32_OR(PMSTS, 1);
+	mchbar32_or(PMSTS, 1);
reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10);
    if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
@@ -566,7 +567,7 @@
    MCHBAR32(HMCCPEXT) = 0;
    MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3];
-	MCHBAR32_OR(HMCCMC, 1 << 7);
+	mchbar32_or(HMCCMC, 1 << 7);
if ((fsb_freq == 0) && (ddr_freq == 1)) {
    	MCHBAR8(CLKXSSH2MCBYPPHAS) = 0;
@@ -616,8 +617,8 @@
    u8  ddr_freq;
    u16 mpll_ctl;
-	MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8));
-	MCHBAR8_AND(CSHRMISCCTL1,  ~0x3f);
+	mchbar16_and(CSHRMISCCTL1, (u16)~(1 << 8));
+	mchbar8_and(CSHRMISCCTL1,  (u8)~0x3f);
if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
    	ddr_freq = 0;
@@ -627,10 +628,10 @@
    	mpll_ctl = (1 << 8) | (1 << 5);
    }
    if (s->boot_path != BOOT_PATH_RESET)
-		MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl);
+		mchbar16_and_or(MPLLCTL, (u16)~(0x033f), mpll_ctl);
MCHBAR32(C0GNT2LNCH1) = 0x58001117;
-	MCHBAR32_OR(C0STATRDCTRL, 1 << 23);
+	mchbar32_or(C0STATRDCTRL, 1 << 23);
const u32 cas_to_reg[2][4] = {
    	{0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */
@@ -682,7 +683,7 @@
    	flag = 1;
    }
-	MCHBAR8_OR(C0PVCFG, 0x03);
+	mchbar8_or(C0PVCFG, 0x03);
    MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) |
    			 ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1;
@@ -699,7 +700,7 @@
/* FIXME: Only applies to DDR2 */
    reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6;
-	MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7));
+	mchbar16_and_or(SHCYCTRKCKEL, (u16)~0x1f80, (reg16 << 7));
reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4;
    MCHBAR16(C0CYCTRKWR) = reg16;
@@ -714,10 +715,10 @@
    MCHBAR8(C0CYCTRKREFR)     = (u8) (reg16);
    MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8);
-	MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1);
-	MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS);
+	mchbar16_and_or(C0CKECTRL, (u16)~0x03fe, 100 << 1);
+	mchbar8_and_or(C0CYCTRKPCHG2, (u8)~0x3f, s->selected_timings.tRAS);
    MCHBAR16(C0ARBCTRL) = 0x2310;
-	MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1);
+	mchbar8_and_or(C0ADDCSCTRL, (u8)~0x1f, 1);
if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
    	reg32 = 3000;
@@ -730,7 +731,7 @@
    	reg2 = 5000;
    }
    reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8);
-	MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16);
+	mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, reg16);
flag = 0;
    if (wl > 2) {
@@ -739,13 +740,13 @@
    reg16 = (u8) (wl - 1 - flag);
    reg16 |= reg16 << 4;
    reg16 |= flag << 8;
-	MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16);
+	mchbar16_and_or(C0WRDATACTRL, (u16)~0x01ff, reg16);
MCHBAR16(C0RDQCTRL) = 0x1585;
-	MCHBAR8_AND(C0PWLRCTRL, ~0x1f);
+	mchbar8_and(C0PWLRCTRL, (u8)~0x1f);
/* rdmodwr_window[5..0] = CL+4+5  265[13..8] (264[21..16]) */
-	MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8);
+	mchbar16_and_or(C0PWLRCTRL, (u16)~0x3f00, (s->selected_timings.CAS + 9) << 8);
if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
    	reg16 = 0x0514;
@@ -754,115 +755,115 @@
    	reg16 = 0x0618;
    	reg32 = 0x0c30;
    }
-	MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8));
+	mchbar32_and_or(C0REFRCTRL2, (u32)~0x0fffff00, (0x3f << 22) | (reg32 << 8));
/* FIXME: Is this weird access necessary? Reference code does it */
    MCHBAR8(C0REFRCTRL + 3) = 0;
-	MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16);
+	mchbar16_and_or(C0REFCTRL, 0xc000, reg16);
/* NPUT Static Mode */
-	MCHBAR8_OR(C0DYNRDCTRL, 1);
+	mchbar8_or(C0DYNRDCTRL, 1);
-	MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25);
+	mchbar32_and_or(C0STATRDCTRL, (u32)~0x7f000000, 0xb << 25);
    i = s->selected_timings.mem_clock;
    j = s->selected_timings.fsb_clock;
    if (i > j) {
-		MCHBAR32_OR(C0STATRDCTRL, 1 << 24);
+		mchbar32_or(C0STATRDCTRL, 1 << 24);
    }
-	MCHBAR8_AND(C0RDFIFOCTRL, ~0x3);
-	MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10);
-	MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17));
+	mchbar8_and(C0RDFIFOCTRL, (u8)~0x3);
+	mchbar16_and_or(C0WRDATACTRL, (u16)~0x7c00, (wl + 10) << 10);
+	mchbar32_and_or(C0CKECTRL, (u32)~0x070e0000, (3 << 24) | (3 << 17));
    reg16 = 0x15 << 6;
    reg16 |= 0x1f;
    reg16 |= (0x6 << 12);
-	MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16);
+	mchbar16_and_or(C0REFRCTRL + 4, (u16)~0x7fff, reg16);
reg32 = (0x6 << 27) | (1 << 25);	/* FIXME: For DDR3, set BIT26 as well */
-	MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8);
-	MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24);
-	MCHBAR8_AND(C0JEDEC, ~(1 << 7));
-	MCHBAR8_AND(C0DYNRDCTRL, ~0x6);
+	mchbar32_and_or(C0REFRCTRL2, (u32)~0x30000000, reg32 << 8);
+	mchbar8_and_or(C0REFRCTRL + 3, (u8)~0xfa, reg32 >> 24);
+	mchbar8_and(C0JEDEC, (u8)~(1 << 7));
+	mchbar8_and(C0DYNRDCTRL, (u8)~0x6);
/* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */
    reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1;
    MCHBAR32(C0WRWMFLSH) = reg32;
-	MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2));
-	MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5));
+	mchbar16_and_or(C0WRWMFLSH + 4, (u16)~0x1ff, (8 << 3) | (6 >> 2));
+	mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5));
/* FIXME: Why not do a single word write? */
-	MCHBAR8_AND_OR(SHPAGECTRL,     ~0xff, 0x40);
-	MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05);
-	MCHBAR8_OR(SHCMPLWRCMD, 0x1f);
+	mchbar8_and_or(SHPAGECTRL, (u8)~0xff, 0x40);
+	mchbar8_and_or(SHPAGECTRL + 1, (u8)~0x07, 0x05);
+	mchbar8_or(SHCMPLWRCMD, 0x1f);
reg8  = (3 << 6);
    reg8 |= (s->dt0mode << 4);
    reg8 |= 0x0c;
-	MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8);
-	MCHBAR8_AND(CSHRWRIOMLNS, ~0x02);
-	MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02);
-	MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2);
+	mchbar8_and_or(SHBONUSREG, (u8)~0xdf, reg8);
+	mchbar8_and(CSHRWRIOMLNS, (u8)~0x02);
+	mchbar8_and_or(C0MISCTM, (u8)~0x07, 0x02);
+	mchbar16_and_or(C0BYPCTRL, (u16)~0x3fc, 4 << 2);
/* [31..29] = 0b010 for kN = 2 (2N) */
    reg32 = (2 << 29) | (1 << 28) | (1 << 23);
-	MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32);
+	mchbar32_and_or(WRWMCONFIG, (u32)~0xffb00000, reg32);
reg8  = (u8) ((MCHBAR16(C0CYCTRKACT)     & 0xe000) >> 13);
    reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3);
-	MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4);
+	mchbar8_and_or(BYPACTSF, (u8)~0xf0, reg8 << 4);
reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17);
-	MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8);
+	mchbar8_and_or(BYPACTSF, (u8)~0x0f, reg8);
/* FIXME: Why not clear everything at once? */
-	MCHBAR8_AND(BYPKNRULE, ~0xfc);
-	MCHBAR8_AND(BYPKNRULE, ~0x03);
-	MCHBAR8_AND(SHBONUSREG, ~0x03);
-	MCHBAR8_OR(C0BYPCTRL, 1);
-	MCHBAR16_OR(CSHRMISCCTL1, 1 << 9);
+	mchbar8_and(BYPKNRULE, (u8)~0xfc);
+	mchbar8_and(BYPKNRULE, (u8)~0x03);
+	mchbar8_and(SHBONUSREG, (u8)~0x03);
+	mchbar8_or(C0BYPCTRL, 1);
+	mchbar16_or(CSHRMISCCTL1, 1 << 9);
for (i = 0; i < 8; i++) {
    	/* FIXME: Hardcoded for DDR2 SO-DIMMs */
-		MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c);
+		mchbar32_and_or(C0DLLRCVCTLy(i), (u32)~0x3f3f3f3f, 0x0c0c0c0c);
    }
    /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */
-	MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16);
+	mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, (s->selected_timings.CAS + 1) << 16);
/* Program RCVEN delay with DLL-safe settings */
    for (i = 0; i < 8; i++) {
-		MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f);
-		MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2)));
-		MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2)));
-		MCHBAR16_AND(C0COARSEDLY0,  (u16) ~(3 << (i * 2)));
+		mchbar8_and(C0RXRCVyDLL(i), (u8)~0x3f);
+		mchbar16_and(C0RCVMISCCTL2, (u16)~(3 << (i * 2)));
+		mchbar16_and(C0RCVMISCCTL1, (u16)~(3 << (i * 2)));
+		mchbar16_and(C0COARSEDLY0,  (u16)~(3 << (i * 2)));
    }
-	MCHBAR8_AND(C0DLLPIEN, ~1);	/* Power up receiver */
-	MCHBAR8_OR(C0DLLPIEN,   2);	/* Enable RCVEN DLL */
-	MCHBAR8_OR(C0DLLPIEN,   4);	/* Enable receiver DQS DLL */
-	MCHBAR32_OR(C0COREBONUS, 0x000c0400);
-	MCHBAR32_OR(C0CMDTX1, 1 << 31);
+	mchbar8_and(C0DLLPIEN, (u8)~1);	/* Power up receiver */
+	mchbar8_or(C0DLLPIEN,   2);	/* Enable RCVEN DLL */
+	mchbar8_or(C0DLLPIEN,   4);	/* Enable receiver DQS DLL */
+	mchbar32_or(C0COREBONUS, 0x000c0400);
+	mchbar32_or(C0CMDTX1, 1 << 31);
 }
/* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */
 static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i)
 {
-	MCHBAR16_AND_OR(C0CKTX, ~0xc440,
+	mchbar16_and_or(C0CKTX, (u16)~0xc440,
    		(pll->clkdelay[f][i] << 14) |
    		(pll->dben[f][i] << 10) |
    		(pll->dbsel[f][i] << 6));
-	MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]);
+	mchbar8_and_or(C0TXCK0DLL, (u8)~0x3f, pll->pi[f][i]);
 }
/* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */
 static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i)
 {
    /* FIXME: This is actually a dword write! */
-	MCHBAR16_AND_OR(C0CKTX, ~0x00030880,
+	mchbar16_and_or(C0CKTX, (u16)~0x00030880,
    		(pll->clkdelay[f][i] << 16) |
    		(pll->dben[f][i] << 11) |
    		(pll->dbsel[f][i] << 7));
-	MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]);
+	mchbar8_and_or(C0TXCK1DLL, (u8)~0x3f, pll->pi[f][i]);
 }
/* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */
@@ -872,14 +873,14 @@
    /* Clock Group Index 3 */
    reg8 = pll->dbsel[f][i] << 5;
    reg8 |= pll->dben[f][i] << 6;
-	MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8);
+	mchbar8_and_or(C0CMDTX1, (u8)~0x60, reg8);
reg8 = pll->clkdelay[f][i] << 4;
-	MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8);
+	mchbar8_and_or(C0CMDTX2, (u8)~0x30, reg8);
reg8 = pll->pi[f][i];
-	MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8);
-	MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8);
+	mchbar8_and_or(C0TXCMD0DLL, (u8)~0x3f, reg8);
+	mchbar8_and_or(C0TXCMD1DLL, (u8)~0x3f, reg8);
 }
/* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */
@@ -895,11 +896,11 @@
    reg32 |= ((u32) pll->dben[f][i])  << 23;
    reg32 |= ((u32) pll->clkdelay[f][i]) << 24;
    reg32 |= ((u32) pll->clkdelay[f][i]) << 27;
-	MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32);
+	mchbar32_and_or(C0CTLTX2, (u32)~0x01bf0000, reg32);
reg8 = pll->pi[f][i];
-	MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8);
-	MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8);
+	mchbar8_and_or(C0TXCTL0DLL, (u8)~0x3f, reg8);
+	mchbar8_and_or(C0TXCTL1DLL, (u8)~0x3f, reg8);
/* CTRL2 and CTRL3 */
    reg32  = ((u32) pll->dbsel[f][i]) << 12;
@@ -908,11 +909,11 @@
    reg32 |= ((u32) pll->dben[f][i])  << 9;
    reg32 |= ((u32) pll->clkdelay[f][i]) << 14;
    reg32 |= ((u32) pll->clkdelay[f][i]) << 10;
-	MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32);
+	mchbar32_and_or(C0CMDTX2, (u32)~0xff00, reg32);
reg8 = pll->pi[f][i];
-	MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8);
-	MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8);
+	mchbar8_and_or(C0TXCTL2DLL, (u8)~0x3f, reg8);
+	mchbar8_and_or(C0TXCTL3DLL, (u8)~0x3f, reg8);
 }
static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
@@ -934,11 +935,11 @@
    			   & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16);
-	MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))),
+	mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))),
    		reg32);
reg8 = pll->pi[f][clk];
-	MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8);
+	mchbar8_and_or(C0TXDQS0R0DLL + j, (u8)~0x3f, reg8);
 }
@@ -961,10 +962,10 @@
    			  & ~((1 << (dq + 9)) | (1 << dq))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
-	MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32);
+	mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32);
reg8 = pll->pi[f][clk];
-	MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8);
+	mchbar8_and_or(C0TXDQ0R0DLL + j, (u8)~0x3f, reg8);
 }
/* WDLL programming: Perform HPLL/MPLL calibration after write levelization */
@@ -1055,8 +1056,8 @@
    }
/* Disable Dynamic DQS Slave Setting Per Rank */
-	MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7));
-	MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff);
+	mchbar8_and(CSHRDQSCMN, (u8)~(1 << 7));
+	mchbar16_and_or(CSHRPDCTL4, (u16)~0x3fff, 0x1fff);
sdram_p_clkset0(&pll, f, 0);
    sdram_p_clkset1(&pll, f, 1);
@@ -1079,13 +1080,13 @@
    s->async = 0;
    reg8 = 0;
-	MCHBAR16_OR(CSHRPDCTL, 1 << 15);
-	MCHBAR8_AND(CSHRPDCTL, ~(1 << 7));
-	MCHBAR8_OR(CSHRPDCTL, 1 << 3);
-	MCHBAR8_OR(CSHRPDCTL, 1 << 2);
+	mchbar16_or(CSHRPDCTL, 1 << 15);
+	mchbar8_and(CSHRPDCTL, (u8)~(1 << 7));
+	mchbar8_or(CSHRPDCTL, 1 << 3);
+	mchbar8_or(CSHRPDCTL, 1 << 2);
/* Start hardware HMC calibration */
-	MCHBAR8_OR(CSHRPDCTL, 1 << 7);
+	mchbar8_or(CSHRPDCTL, 1 << 7);
/* Busy-wait until calibration is done */
    while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0)
@@ -1110,80 +1111,80 @@
    } else {
    	reg32 = 0x00014221;
    }
-	MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32);
-	MCHBAR32_OR(CSHRMSTRCTL1,    1 << 23);
-	MCHBAR32_OR(CSHRMSTRCTL1,    1 << 15);
-	MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15));
+	mchbar32_and_or(CSHRMSTRCTL1, (u32)~0x0fffffff, reg32);
+	mchbar32_or(CSHRMSTRCTL1,    1 << 23);
+	mchbar32_or(CSHRMSTRCTL1,    1 << 15);
+	mchbar32_and(CSHRMSTRCTL1, (u32)~(1 << 15));
if (s->nodll) {
    	/* Disable the Master DLLs by setting these bits, IN ORDER! */
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12);
-		MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 0);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 2);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 4);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 8);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 10);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 12);
+		mchbar16_or(CSHRMSTRCTL0, 1 << 14);
    } else {
    	/* Enable the Master DLLs by clearing these bits, IN ORDER! */
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 <<  0));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 <<  2));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 <<  4));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 <<  8));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12));
-		MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 <<  0));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 <<  2));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 <<  4));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 <<  8));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 10));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 12));
+		mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 14));
    }
/* Initialize the Transmit DLL PI values in the following sequence. */
    if (s->nodll) {
-		MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07);
+		mchbar8_and_or(CREFPI, (u8)~0x3f, 0x07);
    } else {
-		MCHBAR8_AND(CREFPI, ~0x3f);
+		mchbar8_and(CREFPI, (u8)~0x3f);
    }
sdram_calibratepll(s, 0); // XXX check
/* Enable all modular Slave DLL */
-	MCHBAR16_OR(C0DLLPIEN, 1 << 11);
-	MCHBAR16_OR(C0DLLPIEN, 1 << 12);
+	mchbar16_or(C0DLLPIEN, 1 << 11);
+	mchbar16_or(C0DLLPIEN, 1 << 12);
for (i = 0; i < 8; i++) {
-		MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i);
+		mchbar16_or(C0DLLPIEN, (1 << 10) >> i);
    }
    /* Enable DQ/DQS output */
-	MCHBAR8_OR(C0SLVDLLOUTEN, 1);
+	mchbar8_or(C0SLVDLLOUTEN, 1);
    MCHBAR16(CSPDSLVWT) = 0x5005;
-	MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a);
-	MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010);
+	mchbar16_and_or(CSHRPDCTL2, (u16)~0x1f1f, 0x051a);
+	mchbar16_and_or(CSHRPDCTL5, (u16)~0xbf3f, 0x9010);
if (s->nodll) {
-		MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b);
+		mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x6b);
    } else {
-		MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55);
+		mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x55);
    	sdram_calibratehwpll(s);
    }
    /* Disable Dynamic Diff Amp */
-	MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22));
+	mchbar32_and(C0STATRDCTRL, (u32)~(1 << 22));
/* Now, start initializing the transmit FIFO */
-	MCHBAR8_AND(C0MISCCTL, ~0x02);
+	mchbar8_and(C0MISCCTL, (u8)~0x02);
/* Disable (gate) mdclk and mdclkb */
-	MCHBAR8_OR(CSHWRIOBONUS, 0xc0);
+	mchbar8_or(CSHWRIOBONUS, 0xc0);
/* Select mdmclk */
-	MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5));
+	mchbar8_and(CSHWRIOBONUS, (u8)~(1 << 5));
/* Ungate mdclk */
-	MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6);
-	MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a);
+	mchbar8_and_or(CSHWRIOBONUS, (u8)~0xc0, 1 << 6);
+	mchbar8_and_or(CSHRFIFOCTL, (u8)~0x3f, 0x1a);
/* Enable the write pointer count */
-	MCHBAR8_OR(CSHRFIFOCTL, 1);
+	mchbar8_or(CSHRFIFOCTL, 1);
/* Set the DDR3 Reset Enable bit */
-	MCHBAR8_OR(CSHRDDR3CTL, 1);
+	mchbar8_or(CSHRDDR3CTL, 1);
/* Configure DQS-DQ Transmit */
    MCHBAR32(CSHRDQSTXPGM) = 0x00551803;
@@ -1191,10 +1192,10 @@
    reg8 = 0; /* Switch all clocks on anyway */
/* Enable clock groups depending on rank population */
-	MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24);
+	mchbar32_and_or(C0CKTX, (u32)~0x3f000000, reg8 << 24);
/* Enable DDR command output buffers from core */
-	MCHBAR8_AND(0x594, ~1);
+	mchbar8_and(0x594, (u8)~1);
reg16 = 0;
    if (!rank_is_populated(s->dimms, 0, 0)) {
@@ -1209,7 +1210,7 @@
    if (!rank_is_populated(s->dimms, 0, 3)) {
    	reg16 |= (1 << 11) | (1 << 7) | (1 << 3);
    }
-	MCHBAR16_OR(C0CTLTX2, reg16);
+	mchbar16_or(C0CTLTX2, reg16);
 }
/* Define a shorter name for these to make the lines fit in 96 characters */
@@ -1344,54 +1345,54 @@
FOR_EACH_RCOMP_GROUP(i) {
    	reg8 = rcompupdate[i];
-		MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8);
-		MCHBAR8_AND(C0RCOMPCTRLx(i), ~2);
+		mchbar8_and_or(C0RCOMPCTRLx(i), (u8)~1, reg8);
+		mchbar8_and(C0RCOMPCTRLx(i), (u8)~2);
reg16 = rcompslew;
-		MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12);
+		mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12);
MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i];
    	MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i];
-		MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]);
+		mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay[i]);
    	if (i == 2) {
    		/* FIXME: Why are we rewriting this? */
-			MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12);
+			mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12);
MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]];
    		MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]];
-			MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]);
+			mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay2[s->dimm_config[0]]);
    	}
-		MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f);
+		mchbar16_and(C0SLEWBASEx(i), (u16)~0x7f7f);
/* FIXME: Why not do a single dword write? */
-		MCHBAR16_AND(C0SLEWPULUTx(i),     ~0x3f3f);
-		MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f);
+		mchbar16_and(C0SLEWPULUTx(i), (u16)~0x3f3f);
+		mchbar16_and(C0SLEWPULUTx(i) + 2, (u16)~0x3f3f);
/* FIXME: Why not do a single dword write? */
-		MCHBAR16_AND(C0SLEWPDLUTx(i),     ~0x3f3f);
-		MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f);
+		mchbar16_and(C0SLEWPDLUTx(i),     (u16)~0x3f3f);
+		mchbar16_and(C0SLEWPDLUTx(i) + 2, (u16)~0x3f3f);
    }
/* FIXME: Hardcoded */
-	MCHBAR8_AND_OR(C0ODTRECORDX,    ~0x3f, 0x36);
-	MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36);
+	mchbar8_and_or(C0ODTRECORDX,    (u8)~0x3f, 0x36);
+	mchbar8_and_or(C0DQSODTRECORDX, (u8)~0x3f, 0x36);
FOR_EACH_RCOMP_GROUP(i) {
-		MCHBAR8_AND(C0RCOMPCTRLx(i),      ~0x60);
-		MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706);
-		MCHBAR16_AND(C0RCOMPOSVx(i),      ~0x7f7f);
-		MCHBAR16_AND(C0SCOMPOFFx(i),      ~0x3f3f);
-		MCHBAR16_AND(C0DCOMPOFFx(i),      ~0x1f1f);
-		MCHBAR8_AND(C0DCOMPOFFx(i) + 2,   ~0x1f);
+		mchbar8_and(C0RCOMPCTRLx(i),      (u8)~0x60);
+		mchbar16_and(C0RCOMPCTRLx(i) + 2, (u16)~0x0706);
+		mchbar16_and(C0RCOMPOSVx(i),      (u16)~0x7f7f);
+		mchbar16_and(C0SCOMPOFFx(i),      (u16)~0x3f3f);
+		mchbar16_and(C0DCOMPOFFx(i),      (u16)~0x1f1f);
+		mchbar8_and(C0DCOMPOFFx(i) + 2,   (u8)~0x1f);
    }
-	MCHBAR16_AND(C0ODTRECORDX,     ~0xffc0);
-	MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f);
+	mchbar16_and(C0ODTRECORDX,     (u16)~0xffc0);
+	mchbar16_and(C0ODTRECORDX + 2, (u16)~0x000f);
/* FIXME: Why not do a single dword write? */
-	MCHBAR16_AND(C0DQSODTRECORDX,     ~0xffc0);
-	MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f);
+	mchbar16_and(C0DQSODTRECORDX,     (u16)~0xffc0);
+	mchbar16_and(C0DQSODTRECORDX + 2, (u16)~0x000f);
FOR_EACH_RCOMP_GROUP(i) {
    	MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i];
@@ -1401,33 +1402,33 @@
    	MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C;
    }
-	MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219);
+	mchbar32_and_or(DCMEASBUFOVR, (u32)~0x001f1f1f, 0x000c1219);
/* FIXME: Why not do a single word write? */
-	MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200);
-	MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12);
+	mchbar16_and_or(XCOMPSDR0BNS, (u16)~0x1f00, 0x1200);
+	mchbar8_and_or(XCOMPSDR0BNS, (u8)~0x1f, 0x12);
MCHBAR32(COMPCTRL3) = 0x007C9007;
    MCHBAR32(OFREQDELSEL) = rcomp1;
    MCHBAR16(XCOMPCMNBNS) = 0x1f7f;
    MCHBAR32(COMPCTRL2) = rcomp2;
-	MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1);
+	mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 1);
    MCHBAR16(ZQCALCTRL) = 0x0134;
    MCHBAR32(COMPCTRL1) = 0x4C293600;
/* FIXME: wtf did these MRC guys smoke */
-	MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2));
-	MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13));
-	MCHBAR8_AND(XCOMPSDR0BNS,  ~(1 <<  5));
+	mchbar8_and_or(COMPCTRL1 + 3, (u8)~0x44, (1 << 6) | (1 << 2));
+	mchbar16_and(XCOMPSDR0BNS, (u16)~(1 << 13));
+	mchbar8_and(XCOMPSDR0BNS,  (u8)~(1 <<  5));
FOR_EACH_RCOMP_GROUP(i) {
    	/* FIXME: This should be an _AND_OR */
-		MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71;
+		MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & (u8)~0x71;
    }
if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) {
    	/* Start COMP */
-		MCHBAR8_OR(COMPCTRL1, 1);
+		mchbar8_or(COMPCTRL1, 1);
/* Wait until COMP is done */
    	while ((MCHBAR8(COMPCTRL1) & 1) != 0)
@@ -1443,55 +1444,55 @@
/* FIXME: Why not do a single word write? */
    		reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8;
-			MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16);
+			mchbar16_and_or(C0SLEWBASEx(i), (u16)~0x7f00, reg16);
reg16 = (u16)(rcompn - (1 << (srun + 1)));
-			MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16);
+			mchbar8_and_or(C0SLEWBASEx(i), (u8)~0x7f, (u8)reg16);
    	}
reg8 = rcompp - (1 << (srup + 1));
    	for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
-			MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]);
+			mchbar8_and_or(C0SLEWPULUTx(0) + i, (u8)~0x3f, rcomplut[j][0]);
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
    		if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) {
-				MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]);
+				mchbar8_and_or(C0SLEWPULUTx(2) + i, (u8)~0x3f, rcomplut[j][10]);
    		}
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
-			MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]);
-			MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]);
+			mchbar8_and_or(C0SLEWPULUTx(3) + i, (u8)~0x3f, rcomplut[j][6]);
+			mchbar8_and_or(C0SLEWPULUTx(4) + i, (u8)~0x3f, rcomplut[j][6]);
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
-			MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]);
-			MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]);
+			mchbar8_and_or(C0SLEWPULUTx(5) + i, (u8)~0x3f, rcomplut[j][8]);
+			mchbar8_and_or(C0SLEWPULUTx(6) + i, (u8)~0x3f, rcomplut[j][8]);
    	}
reg8 = rcompn - (1 << (srun + 1));
    	for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
-			MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]);
+			mchbar8_and_or(C0SLEWPDLUTx(0) + i, (u8)~0x3f, rcomplut[j][1]);
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
    		if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) {
-				MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]);
+				mchbar8_and_or(C0SLEWPDLUTx(2) + i, (u8)~0x3f, rcomplut[j][11]);
    		}
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
-			MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]);
-			MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]);
+			mchbar8_and_or(C0SLEWPDLUTx(3) + i, (u8)~0x3f, rcomplut[j][7]);
+			mchbar8_and_or(C0SLEWPDLUTx(4) + i, (u8)~0x3f, rcomplut[j][7]);
    	}
for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
-			MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]);
-			MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]);
+			mchbar8_and_or(C0SLEWPDLUTx(5) + i, (u8)~0x3f, rcomplut[j][9]);
+			mchbar8_and_or(C0SLEWPDLUTx(6) + i, (u8)~0x3f, rcomplut[j][9]);
    	}
    }
-	MCHBAR8_OR(COMPCTRL1, 1);
+	mchbar8_or(COMPCTRL1, 1);
 }
/* FIXME: The ODT tables are for DDR2 only! */
@@ -1566,24 +1567,24 @@
    if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) {
    	if (s->dimms[0].sides > 1) {
    		// 2R/NC
-			MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001);
+			mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001);
    		MCHBAR32(C0DRA01) = 0x00000101;
    		MCHBAR32(C0DRB0)  = 0x00040002;
    		MCHBAR32(C0DRB2)  = w204[s->dimm_config[0]];
    	} else {
    		// 1R/NC
-			MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001);
+			mchbar32_and_or(C0CKECTRL, (u32)~1, 0x100001);
    		MCHBAR32(C0DRA01) = 0x00000001;
    		MCHBAR32(C0DRB0)  = 0x00020002;
    		MCHBAR32(C0DRB2)  = w204[s->dimm_config[0]];
    	}
    } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) {
-		MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001);
+		mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001);
    	MCHBAR32(C0DRA01) = 0x00000101;
    	MCHBAR32(C0DRB0)  = 0x00040002;
    	MCHBAR32(C0DRB2)  = 0x00040004;
    } else {
-		MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]);
+		mchbar32_and_or(C0CKECTRL, (u32)~1, w260[s->dimm_config[0]]);
    	MCHBAR32(C0DRA01) = w208[s->dimm_config[0]];
    	MCHBAR32(C0DRB0)  = w200[s->dimm_config[0]];
    	MCHBAR32(C0DRB2)  = w204[s->dimm_config[0]];
@@ -1652,10 +1653,10 @@
    u32 reg32a, reg32b;
ok = 0;
-	MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3));
-	MCHBAR8_AND(COMPCTRL1, ~(1 << 7));
+	mchbar8_and(XCOMPDFCTRL, (u8)~(1 << 3));
+	mchbar8_and(COMPCTRL1, (u8)~(1 << 7));
    for (i = 0; i < 3; i++) {
-		MCHBAR8_OR(COMPCTRL1, 1);
+		mchbar8_or(COMPCTRL1, 1);
    	hpet_udelay(1000);
    	while ((MCHBAR8(COMPCTRL1) & 1) != 0)
    		;
@@ -1668,7 +1669,7 @@
    	reg32a |= (1 << 31) | (1 << 15);
    	MCHBAR32(RCMEASBUFXOVR) = reg32a;
    }
-	MCHBAR8_OR(COMPCTRL1, 1);
+	mchbar8_or(COMPCTRL1, 1);
    hpet_udelay(1000);
    while ((MCHBAR8(COMPCTRL1) & 1) != 0)
    	;
@@ -1681,7 +1682,7 @@
reg32 = jval << 3;
    reg32 |= rank * (1 << 27);
-	MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode);
+	mchbar8_and_or(C0JEDEC, (u8)~0x3e, jmode);
    read32((void *)reg32);
    barrier();
    hpet_udelay(1); // 1us
@@ -1690,10 +1691,10 @@
 static void sdram_zqcl(struct sysinfo *s)
 {
    if (s->boot_path == BOOT_PATH_RESUME) {
-		MCHBAR32_OR(C0CKECTRL, 1 << 27);
-		MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD);
-		MCHBAR8_AND(C0JEDEC, ~0x30);
-		MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30);
+		mchbar32_or(C0CKECTRL, 1 << 27);
+		mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD);
+		mchbar8_and(C0JEDEC, (u8)~0x30);
+		mchbar32_and_or(C0REFRCTRL2, (u32)~(3 << 30), 3 << 30);
    }
 }
@@ -1759,12 +1760,12 @@
    reg32 = 0;
    reg32 |= (4 << 13);
    reg32 |= (6 <<  8);
-	MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32);
-	MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7));
-	MCHBAR8_OR(C0REFRCTRL + 3, 1);
+	mchbar32_and_or(C0DYNRDCTRL, (u32)~0x3ff00, reg32);
+	mchbar8_and(C0DYNRDCTRL, (u8)~(1 << 7));
+	mchbar8_or(C0REFRCTRL + 3, 1);
    if (s->boot_path != BOOT_PATH_RESUME) {
-		MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD);
-		MCHBAR8_AND(C0JEDEC, ~0x30);
+		mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD);
+		mchbar8_and(C0JEDEC, (u8)~0x30);
    } else {
    	sdram_zqcl(s);
    }
@@ -1861,10 +1862,10 @@
    	reg32 |= (1 << r);
    }
    reg8 = (u8)(reg32 << 4) & 0xf0;
-	MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8);
+	mchbar8_and_or(C0CKECTRL + 2, (u8)~0xf0, reg8);
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) {
-		MCHBAR8_OR(C0CKECTRL, 1);
+		mchbar8_or(C0CKECTRL, 1);
    }
addr = C0DRB0;
@@ -1885,9 +1886,9 @@
 {
    u8 dqsmatches = 1;
    while (count--) {
-		MCHBAR8_AND(C0RSTCTL, ~2);
+		mchbar8_and(C0RSTCTL, (u8)~2);
    	hpet_udelay(1);
-		MCHBAR8_OR(C0RSTCTL, 2);
+		mchbar8_or(C0RSTCTL, 2);
    	hpet_udelay(1);
    	barrier();
    	read32((void *)strobeaddr);
@@ -1906,12 +1907,12 @@
 {
    if (*medium < 3) {
    	(*medium)++;
-		MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2));
+		mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2));
    } else {
    	*medium = 0;
    	(*coarse)++;
-		MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16);
-		MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2));
+		mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, *coarse << 16);
+		mchbar16_and_or(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2));
    }
 }
@@ -1930,8 +1931,8 @@
    u32 strobeaddr = 0;
    u32 dqshighaddr;
-	MCHBAR8_AND(C0RSTCTL, ~0x0c);
-	MCHBAR8_AND(CMNDQFIFORST, ~0x80);
+	mchbar8_and(C0RSTCTL, (u8)~0x0c);
+	mchbar8_and(CMNDQFIFORST, (u8)~0x80);
PRINTK_DEBUG("rcven 0\n");
    for (lane = 0; lane < maxlane; lane++) {
@@ -1943,10 +1944,10 @@
    	pi = 0;
    	medium = 0;
-		MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16);
-		MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2));
+		mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16);
+		mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2));
-		MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f);
+		mchbar8_and(C0RXRCVyDLL(lane), (u8)~0x3f);
savecoarse = coarse;
    	savemedium = medium;
@@ -1955,7 +1956,7 @@
    	PRINTK_DEBUG("rcven 0.1\n");
// XXX comment out
-		// MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2));
+		// mchbar16_and_or(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2));
while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) {
    		// printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium);
@@ -1986,8 +1987,8 @@
    	PRINTK_DEBUG("rcven 0.3\n");
    	coarse = savecoarse;
    	medium = savemedium;
-		MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16);
-		MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2));
+		mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16);
+		mchbar16_and_or(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2));
while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) {
    		savepi = pi;
@@ -1998,12 +1999,12 @@
    				break;
    			// }
    		}
-			MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset);
+			mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset);
    	}
    	PRINTK_DEBUG("rcven 0.4\n");
pi = savepi;
-		MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset);
+		mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset);
    	rcvenclock(&coarse, &medium, lane);
if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) {
@@ -2013,7 +2014,7 @@
    	PRINTK_DEBUG("rcven 0.5\n");
    	while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) {
    		coarse--;
-			MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16);
+			mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16);
    		if (coarse == 0) {
    			PRINTK_DEBUG("Error: DQS did not hit 0\n");
    			break;
@@ -2040,10 +2041,10 @@
    do {
    	lane--;
    	offset = lanecoarse[lane] - minlanecoarse;
-		MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2));
+		mchbar16_and_or(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2));
    } while (lane != 0);
-	MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16);
+	mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, minlanecoarse << 16);
s->coarsectrl   = minlanecoarse;
    s->coarsedelay  = MCHBAR16(C0COARSEDLY0);
@@ -2051,14 +2052,14 @@
    s->readptrdelay = MCHBAR16(C0RCVMISCCTL1);
PRINTK_DEBUG("rcven 2\n");
-	MCHBAR8_AND(C0RSTCTL, ~0x0e);
-	MCHBAR8_OR(C0RSTCTL,   0x02);
-	MCHBAR8_OR(C0RSTCTL,   0x04);
-	MCHBAR8_OR(C0RSTCTL,   0x08);
+	mchbar8_and(C0RSTCTL, (u8)~0x0e);
+	mchbar8_or(C0RSTCTL,   0x02);
+	mchbar8_or(C0RSTCTL,   0x04);
+	mchbar8_or(C0RSTCTL,   0x08);
-	MCHBAR8_OR(CMNDQFIFORST,   0x80);
-	MCHBAR8_AND(CMNDQFIFORST, ~0x80);
-	MCHBAR8_OR(CMNDQFIFORST,   0x80);
+	mchbar8_or(CMNDQFIFORST,   0x80);
+	mchbar8_and(CMNDQFIFORST, (u8)~0x80);
+	mchbar8_or(CMNDQFIFORST,   0x80);
    PRINTK_DEBUG("rcven 3\n");
 }
@@ -2138,20 +2139,20 @@
 {
    u8 reg8, ch, r, fsb_freq, ddr_freq;
    u32 mask32, reg32;
-	MCHBAR8_OR(C0ADDCSCTRL, 1);
-	MCHBAR8_OR(C0REFRCTRL + 3, 1);
+	mchbar8_or(C0ADDCSCTRL, 1);
+	mchbar8_or(C0REFRCTRL + 3, 1);
    mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f;
    reg32  = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10;
-	MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32);
+	mchbar32_and_or(WRWMCONFIG, (u32)~mask32, reg32);
    MCHBAR8(C0DITCTRL + 1)  = 2;
    MCHBAR16(C0DITCTRL + 2) = 0x0804;
    MCHBAR16(C0DITCTRL + 4) = 0x2010;
    MCHBAR8(C0DITCTRL + 6)  = 0x40;
    MCHBAR16(C0DITCTRL + 8) = 0x091c;
    MCHBAR8(C0DITCTRL + 10) = 0xf2;
-	MCHBAR8_OR(C0BYPCTRL, 1);
-	MCHBAR8_OR(C0CWBCTRL, 1);
-	MCHBAR16_OR(C0ARBSPL, 0x0100);
+	mchbar8_or(C0BYPCTRL, 1);
+	mchbar8_or(C0CWBCTRL, 1);
+	mchbar16_or(C0ARBSPL, 0x0100);
pci_or_config8(HOST_BRIDGE, 0xf0, 1);
    MCHBAR32(SBCTL)  = 0x00000002;
@@ -2162,7 +2163,7 @@
    MCHBAR32(HIT2) = 0x07000000;
    MCHBAR32(HIT3) = 0x01014010;
    MCHBAR32(HIT4) = 0x0f038000;
-	pci_and_config8(HOST_BRIDGE, 0xf0, ~1);
+	pci_and_config8(HOST_BRIDGE, 0xf0, (u8)~1);
u32 nranks, curranksize, maxranksize, dra;
    u8 rankmismatch;
@@ -2209,14 +2210,14 @@
    	die("Invalid number of ranks found, halt\n");
    	break;
    }
-	MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc);
-	MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000);
+	mchbar8_and_or(CHDECMISC, (u8)~0xfc, reg8 & 0xfc);
+	mchbar32_and(NOACFGBUSCTL, (u32)~0x80000000);
MCHBAR32(HTBONUS0) = 0x0000000f;
-	MCHBAR8_OR(C0COREBONUS + 4, 1);
+	mchbar8_or(C0COREBONUS + 4, 1);
-	MCHBAR32_AND(HIT3, ~0x0e000000);
-	MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000);
+	mchbar32_and(HIT3, (u32)~0x0e000000);
+	mchbar32_and_or(HIT4, (u32)~0x000c0000, 0x00040000);
u32 clkcx[2][2][3] = {
    {
@@ -2236,20 +2237,20 @@
    MCHBAR32(CLKXSSH2X2MD + 4)  = clkcx[fsb_freq][ddr_freq][1];
    MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2];
-	MCHBAR8_AND(HIT4, ~0x02);
+	mchbar8_and(HIT4, (u8)~0x02);
 }
static void sdram_periodic_rcomp(void)
 {
-	MCHBAR8_AND(COMPCTRL1, ~0x02);
+	mchbar8_and(COMPCTRL1, (u8)~0x02);
    while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) {
    	;
    }
-	MCHBAR16_AND(CSHRMISCCTL, ~0x3000);
-	MCHBAR8_OR(CMNDQFIFORST, 0x80);
-	MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09);
+	mchbar16_and(CSHRMISCCTL, (u16)~0x3000);
+	mchbar8_or(CMNDQFIFORST, 0x80);
+	mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 0x09);
-	MCHBAR8_OR(COMPCTRL1, 0x82);
+	mchbar8_or(COMPCTRL1, 0x82);
 }
static void sdram_new_trd(struct sysinfo *s)
@@ -2337,7 +2338,7 @@
    	}
    }
-	MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8);
+	mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, trd << 8);
 }
static void sdram_powersettings(struct sysinfo *s)
@@ -2347,26 +2348,26 @@
/* Thermal sensor */
    MCHBAR8(TSC1) = 0x9b;
-	MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00);
+	mchbar32_and_or(TSTTP, (u32)~0x00ffffff, 0x1d00);
    MCHBAR8(THERM1) = 0x08;
    MCHBAR8(TSC3) = 0x00;
-	MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04);
-	MCHBAR8_AND_OR(THERM1, ~1, 1);
-	MCHBAR8_AND_OR(TCO, ~0x80, 0x80);
+	mchbar8_and_or(TSC2, (u8)~0x0f, 0x04);
+	mchbar8_and_or(THERM1, (u8)~1, 1);
+	mchbar8_and_or(TCO, (u8)~0x80, 0x80);
/* Clock gating */
-	MCHBAR32_AND(PMMISC, ~0x00040001);
-	MCHBAR8_AND(SBCTL3   + 3, ~0x80);
-	MCHBAR8_AND(CISDCTRL + 3, ~0x80);
-	MCHBAR16_AND(CICGDIS, ~0x1fff);
-	MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff);
-	MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06);
-	MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20);
-	MCHBAR8_AND(TSMISC, ~1);
+	mchbar32_and(PMMISC, (u32)~0x00040001);
+	mchbar8_and(SBCTL3   + 3, (u8)~0x80);
+	mchbar8_and(CISDCTRL + 3, (u8)~0x80);
+	mchbar16_and(CICGDIS, (u16)~0x1fff);
+	mchbar32_and(SBCLKGATECTRL, (u32)~0x0001ffff);
+	mchbar16_and(HICLKGTCTL, (u16)~0x03ff & 0x06);
+	mchbar32_and_or(HTCLKGTCTL, (u32)~0xffffffff, 0x20);
+	mchbar8_and(TSMISC, (u8)~1);
    MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15;
-	MCHBAR16_AND_OR(CLOCKGATINGI,  ~0x07fc, 0x0040);
-	MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00);
-	MCHBAR16_AND(CLOCKGATINGIII,   ~0x0d80);
+	mchbar16_and_or(CLOCKGATINGI,  (u16)~0x07fc, 0x0040);
+	mchbar16_and_or(CLOCKGATINGII, (u16)~0x0fff, 0x0d00);
+	mchbar16_and(CLOCKGATINGIII,   (u16)~0x0d80);
    MCHBAR16(GTDPCGC + 2) = 0xffff;
/* Sequencing */
@@ -2379,15 +2380,15 @@
    MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078;
if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz)
-		MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8);
+		mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x00c8);
    else
-		MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100);
+		mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x0100);
j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1;
-	MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700);
-	MCHBAR8_AND_OR(PMPXPRC,  ~0x07, 1);
-	MCHBAR8_AND(PMBAK, ~0x02);
+	mchbar32_and_or(PMCLKRC, (u32)~0x01fff37f, 0x10810700);
+	mchbar8_and_or(PMPXPRC,  (u8)~0x07, 1);
+	mchbar8_and(PMBAK, (u8)~0x02);
static const u16 ddr2lut[2][4][2] = {
    {
@@ -2407,8 +2408,8 @@
    MCHBAR16(C0C2REG)  = 0x7a89;
    MCHBAR8(SHC2REGII) = 0xaa;
    MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1];
-	MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]);
-	MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000);
+	mchbar16_and_or(SHC2REGI, (u16)~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]);
+	mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, 0xf000);
    MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4);
reg32 = s->nodll ? 0x30000000 : 0;
@@ -2416,72 +2417,72 @@
    /* FIXME: Compacting this results in changes to the binary */
    MCHBAR32(C0COREBONUS)  = (MCHBAR32(C0COREBONUS)  & ~0x0f000000) | 0x20000000 | reg32;
-	MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000);
-	MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20);
-	MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b);
+	mchbar32_and_or(CLOCKGATINGI, (u32)~0x00f00000, 0x00f00000);
+	mchbar32_and_or(CLOCKGATINGII - 1, (u32)~0x001ff000, 0xbf << 20);
+	mchbar16_and_or(SHC3C4REG2, (u16)~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b);
    MCHBAR16(SHC3C4REG3) = 0x3264;
-	MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a);
+	mchbar16_and_or(SHC3C4REG4, (u16)~0x3f3f, (0x14 << 8) | 0x0a);
-	MCHBAR32_OR(C1COREBONUS, 0x80002000);
+	mchbar32_or(C1COREBONUS, 0x80002000);
 }
static void sdram_programddr(void)
 {
-	MCHBAR16_AND_OR(CLOCKGATINGII,  ~0x03ff, 0x0100);
-	MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010);
-	MCHBAR16_AND_OR(CLOCKGATINGI,   ~0x7000, 0x2000);
+	mchbar16_and_or(CLOCKGATINGII,  (u16)~0x03ff, 0x0100);
+	mchbar16_and_or(CLOCKGATINGIII, (u16)~0x003f, 0x0010);
+	mchbar16_and_or(CLOCKGATINGI,   (u16)~0x7000, 0x2000);
-	MCHBAR8_AND(CSHRPDCTL,     ~0x0e);
-	MCHBAR8_AND(CSHRWRIOMLNS,  ~0x0c);
-	MCHBAR8_AND(C0MISCCTLy(0), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(1), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(2), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(3), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(4), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(5), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(6), ~0x0e);
-	MCHBAR8_AND(C0MISCCTLy(7), ~0x0e);
-	MCHBAR8_AND(CSHRWRIOMLNS,  ~0x02);
+	mchbar8_and(CSHRPDCTL,     (u8)~0x0e);
+	mchbar8_and(CSHRWRIOMLNS,  (u8)~0x0c);
+	mchbar8_and(C0MISCCTLy(0), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(1), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(2), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(3), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(4), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(5), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(6), (u8)~0x0e);
+	mchbar8_and(C0MISCCTLy(7), (u8)~0x0e);
+	mchbar8_and(CSHRWRIOMLNS,  (u8)~0x02);
-	MCHBAR16_AND(CSHRMISCCTL, ~0x0400);
-	MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0);
-	MCHBAR8_AND(C0WRDPYN, ~0x80);
-	MCHBAR32_AND(C0COREBONUS, ~(1 << 22));
-	MCHBAR16_AND(CLOCKGATINGI,  ~0x80fc);
-	MCHBAR16_AND(CLOCKGATINGII, ~0x0c00);
+	mchbar16_and(CSHRMISCCTL, (u16)~0x0400);
+	mchbar16_and(CLOCKGATINGIII, (u16)~0x0dc0);
+	mchbar8_and(C0WRDPYN, (u8)~0x80);
+	mchbar32_and(C0COREBONUS, (u32)~(1 << 22));
+	mchbar16_and(CLOCKGATINGI,  (u16)~0x80fc);
+	mchbar16_and(CLOCKGATINGII, (u16)~0x0c00);
-	MCHBAR8_AND(CSHRPDCTL,     ~0x0d);
-	MCHBAR8_AND(C0MISCCTLy(0), ~1);
-	MCHBAR8_AND(C0MISCCTLy(1), ~1);
-	MCHBAR8_AND(C0MISCCTLy(2), ~1);
-	MCHBAR8_AND(C0MISCCTLy(3), ~1);
-	MCHBAR8_AND(C0MISCCTLy(4), ~1);
-	MCHBAR8_AND(C0MISCCTLy(5), ~1);
-	MCHBAR8_AND(C0MISCCTLy(6), ~1);
-	MCHBAR8_AND(C0MISCCTLy(7), ~1);
+	mchbar8_and(CSHRPDCTL, (u8)~0x0d);
+	mchbar8_and(C0MISCCTLy(0), (u8)~1);
+	mchbar8_and(C0MISCCTLy(1), (u8)~1);
+	mchbar8_and(C0MISCCTLy(2), (u8)~1);
+	mchbar8_and(C0MISCCTLy(3), (u8)~1);
+	mchbar8_and(C0MISCCTLy(4), (u8)~1);
+	mchbar8_and(C0MISCCTLy(5), (u8)~1);
+	mchbar8_and(C0MISCCTLy(6), (u8)~1);
+	mchbar8_and(C0MISCCTLy(7), (u8)~1);
-	MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20);
-	MCHBAR32_AND(C0COREBONUS, ~0x00100000);
-	MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e);
-	MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03);
-	MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000);
-	MCHBAR16_OR(C0STATRDCTRL, 0x6000);
-	MCHBAR32_OR(C0CKECTRL, 0x00010000);
-	MCHBAR8_OR(C0COREBONUS, 0x10);
-	MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24);
-	MCHBAR8_OR(CSHWRIOBONUS, 0x07);
-	MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0);
-	MCHBAR8_OR(SHC2REGIII, 7);
-	MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080);
-	MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10);
-	MCHBAR16_OR(C0COREBONUS, 0x01e0);
-	MCHBAR8_OR(CSHWRIOBONUS, 0x18);
-	MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d);
-	MCHBAR16_OR(SHC3C4REG1, 0x0a3f);
-	MCHBAR8_OR(C0STATRDCTRL, 3);
-	MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a);
-	MCHBAR8_AND(C0COREBONUS + 4, ~0x60);
-	MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321);
+	mchbar32_and_or(C0STATRDCTRL, (u32)~0x00700000, 3 << 20);
+	mchbar32_and(C0COREBONUS, (u32)~0x00100000);
+	mchbar8_or(C0DYNSLVDLLEN, 0x1e);
+	mchbar8_or(C0DYNSLVDLLEN2, 0x03);
+	mchbar32_and_or(SHCYCTRKCKEL, (u32)~0x0c000000, 0x04000000);
+	mchbar16_or(C0STATRDCTRL, 0x6000);
+	mchbar32_or(C0CKECTRL, 0x00010000);
+	mchbar8_or(C0COREBONUS, 0x10);
+	mchbar32_or(CLOCKGATINGI - 1, 0xf << 24);
+	mchbar8_or(CSHWRIOBONUS, 0x07);
+	mchbar8_or(C0DYNSLVDLLEN, 0xc0);
+	mchbar8_or(SHC2REGIII, 7);
+	mchbar16_and_or(SHC2MINTM, (u16)~0xffff, 0x0080);
+	mchbar8_and_or(SHC2IDLETM, (u8)~0xff, 0x10);
+	mchbar16_or(C0COREBONUS, 0x01e0);
+	mchbar8_or(CSHWRIOBONUS, 0x18);
+	mchbar8_or(CSHRMSTDYNDLLENB, 0x0d);
+	mchbar16_or(SHC3C4REG1, 0x0a3f);
+	mchbar8_or(C0STATRDCTRL, 3);
+	mchbar8_and_or(C0REFRCTRL2, (u8)~0xff, 0x4a);
+	mchbar8_and(C0COREBONUS + 4, (u8)~0x60);
+	mchbar16_or(C0DYNSLVDLLEN, 0x0321);
 }
static void sdram_programdqdqs(struct sysinfo *s)
@@ -2541,13 +2542,13 @@
if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) {
    		if (repeat == 2) {
-				MCHBAR32_AND(C0COREBONUS, ~(1 << 23));
+				mchbar32_and(C0COREBONUS, (u32)~(1 << 23));
    		}
    		feature = 1;
    		repeat = 0;
    	} else {
    		repeat--;
-			MCHBAR32_OR(C0COREBONUS, 1 << 23);
+			mchbar32_or(C0COREBONUS, 1 << 23);
    		cwb = 2 * mdclk;
    	}
    }
@@ -2556,10 +2557,10 @@
    	MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3;
    	return;
    }
-	MCHBAR8_OR(CLOCKGATINGI, 3);
-	MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12);
-	MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push);
-	MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000);
+	mchbar8_or(CLOCKGATINGI, 3);
+	mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, pimdclk << 12);
+	mchbar8_and_or(CSHWRIOBONUSX, (u8)~0x77, (push << 4) | push);
+	mchbar32_and_or(C0COREBONUS, (u32)~0x0f000000, 0x03000000);
 }
/**
@@ -2592,7 +2593,7 @@
    /* Enable HPET */
    enable_hpet();
-	MCHBAR16_OR(CPCTL, 1 << 15);
+	mchbar16_or(CPCTL, 1 << 15);
sdram_clk_crossing(&si);
@@ -2627,16 +2628,16 @@
    PRINTK_DEBUG("Done mmap\n");
/* Enable DDR IO buffer */
-	MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08);
-	MCHBAR8_OR(C0RSTCTL, 1);
+	mchbar8_and_or(C0IOBUFACTCTL, (u8)~0x3f, 0x08);
+	mchbar8_or(C0RSTCTL, 1);
sdram_rcompupdate(&si);
    PRINTK_DEBUG("Done RCOMP update\n");
-	MCHBAR8_OR(HIT4, 2);
+	mchbar8_or(HIT4, 2);
if (si.boot_path != BOOT_PATH_RESUME) {
-		MCHBAR32_OR(C0CKECTRL, 1 << 27);
+		mchbar32_or(C0CKECTRL, 1 << 27);
sdram_jedecinit(&si);
    	PRINTK_DEBUG("Done MRS\n");
@@ -2649,7 +2650,7 @@
    PRINTK_DEBUG("Done zqcl\n");
if (si.boot_path != BOOT_PATH_RESUME) {
-		MCHBAR32_OR(C0REFRCTRL2, 3 << 30);
+		mchbar32_or(C0REFRCTRL2, 3 << 30);
    }
sdram_dradrb(&si);
@@ -2680,7 +2681,7 @@
    PRINTK_DEBUG("Done periodic RCOMP\n");
/* Set init done */
-	MCHBAR32_OR(C0REFRCTRL2, 1 << 30);
+	mchbar32_or(C0REFRCTRL2, 1 << 30);
/* Tell ICH7 that we're done */
    pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7));
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/45517
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5
Gerrit-Change-Number: 45517
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    

Change in coreboot[master]: nb/intel/pineview: Use new mchbar{8,16,32}_and_or()