Change in coreboot[master]: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40790 )
Change subject: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register ......................................................................
util/intelmetool: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/intelmetool/me.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/40790/1
diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index ee2b46a..e9aa510 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -574,7 +574,7 @@ uint32_t intel_mei_setup(struct pci_dev *dev) { struct mei_csr host; - uint32_t reg32; + uint16_t reg16; uint32_t pagerounded;
mei_base_address = dev->base_addr[0] & ~0xf; @@ -588,9 +588,9 @@ }
/* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_long(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_long(dev, PCI_COMMAND, reg32); + reg16 = pci_read_word(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_word(dev, PCI_COMMAND, reg16);
/* Clean up status for next message */ read_host_csr(&host);
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40790 )
Change subject: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40790 )
Change subject: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register ......................................................................
util/intelmetool: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40790 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M util/intelmetool/me.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index ee2b46a..e9aa510 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -574,7 +574,7 @@ uint32_t intel_mei_setup(struct pci_dev *dev) { struct mei_csr host; - uint32_t reg32; + uint16_t reg16; uint32_t pagerounded;
mei_base_address = dev->base_addr[0] & ~0xf; @@ -588,9 +588,9 @@ }
/* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_long(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_long(dev, PCI_COMMAND, reg32); + reg16 = pci_read_word(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_word(dev, PCI_COMMAND, reg16);
/* Clean up status for next message */ read_host_csr(&host);
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)