[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Saurabh Mishra (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 33:

(3 comments)

File src/soc/intel/pantherlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/83354/comment/dfbc037c_796f4f0b?usp... :
PS32, Line 3: #include <arch/cpu.h>
> duplicated as <cpu/cpu.h> is supposed to provide <arch/cpu.h> […]

Acknowledged

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/5eb845ca_236f2e16?usp... :
PS32, Line 19: #define SAF_BASE_ADDRESS	0xfa000000
> > As per latest FAS, SAF BASE address is 0xfa000000. […]

Hi Subrata, there is a FAS v1.1, the SAF is placed to 0xfa000000. Previous SAF(Above 4GB) in v0.5 is now replaced with hole.

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/69c454c7_37495d32?usp... :
PS32, Line 45:  SMI_STS_BITS			32
             : #define  XHCI_SMI_STS_BIT		31
             : #define  ME_SMI_STS_BIT			30
             : #define  ESPI_SMI_STS_BIT		28
             : #define  GPIO_UNLOCK_SMI_STS_BIT	27
             : #define  SPI_SMI_STS_BIT		26
             : #define  SCC_SMI_STS_BIT		25
             : #define  MONITOR_STS_BIT		21
             : #define  PCI_EXP_SMI_STS_BIT		20
> why not here as well

Acknowledged