Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT support on jasperlake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/1
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 78fec88..d355201 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -39,7 +39,45 @@ }, }"
+ register "tcc_offset" = "20" # TCC of 80C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""5V"" + register "options.tsr[3].desc" = ""Charger"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 10000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 60000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 45, 15000)" + register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 50, 15000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 50, 15000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN)" + register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#2).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT support on jasperlake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@9 PS2, Line 9: Add DTT support on jasperlake based drawcia system. : Add information on sensors, power limits and tcc_offset : for DTT based thermal control. : reflow for 72 chars
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@9 PS2, Line 9: jasperlake Jasper Lake
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@11 PS2, Line 11: DTT Write it out once?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#3).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/3
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@9 PS2, Line 9: jasperlake
Jasper Lake
Ack
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@11 PS2, Line 11: DTT
Write it out once?
Done
https://review.coreboot.org/c/coreboot/+/44148/2//COMMIT_MSG@9 PS2, Line 9: Add DTT support on jasperlake based drawcia system. : Add information on sensors, power limits and tcc_offset : for DTT based thermal control. :
reflow for 72 chars
Ack
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#4).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 4: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/4/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/4/src/mainboard/google/dedede... PS4, Line 51: 5V regulator Is it the same as FIVR? If so, dedede has not enabled it.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/4/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/4/src/mainboard/google/dedede... PS4, Line 51: 5V regulator
Is it the same as FIVR? If so, dedede has not enabled it.
As mentioned in schematics, it seems there is temperature sensor placed near 5V IC & choke. Using the same here. Even I see the similar temperature sensor details on ectool.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#5).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/5
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#6).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/6
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/6/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/6/src/mainboard/google/dedede... PS6, Line 43: 4.8 `tdp_pl1_override` is a uint16_t
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#7).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/7
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/6/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/6/src/mainboard/google/dedede... PS6, Line 43: 4.8
`tdp_pl1_override` is a uint16_t
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: , Given that we have slashed 1/3rd of target TDP, how much is performance going to be impacted with this TDP?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
Given that we have slashed 1/3rd of target TDP, how much is performance going to be impacted with th […]
This is being discussed in b:161993459 c#5,7.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
This is being discussed in b:161993459 c#5,7.
The discussion in that bug is based on 4.8 W. Now we have cut it down further because of integer rounding. The bug needs to be updated.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
The discussion in that bug is based on 4.8 W. […]
Ack
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#8).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=b:161993459 TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/8
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
Ack
Once DPTF begins, if temperature allows, it can drive PL1 up to 4.8 (lines 71-72), at a rate of 200 mW / second 😊
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 8: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
Once DPTF begins, if temperature allows, it can drive PL1 up to 4. […]
It seems MSR_PKG_POWER_SKU_UNIT can be configured to some mW. But I am not finding the description of that MSR in any of the documents I have access to.
May not be for this CL. But is it possible to look into it in a follow-up CL?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44148
to look at the new patch set (#9).
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=b:161993459 TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/9
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44148/7/src/mainboard/google/dedede... PS7, Line 43: ,
It seems MSR_PKG_POWER_SKU_UNIT can be configured to some mW. […]
As per latest c#33, updated value here.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 9: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
Patch Set 9: Code-Review+2
Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44148 )
Change subject: mb/google/dedede/variants/drawcia: add DTT support ......................................................................
mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control.
BRANCH=None BUG=b:161993459 TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 78fec88..447d3bc 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -39,7 +39,50 @@ }, }"
+ register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, + }" + + register "tcc_offset" = "20" # TCC of 85C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)" + register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 1000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN)" + register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 6000, + .max_power = 15000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on
-
Karthik Ramasubramanian (Code Review) -
Paul Menzel (Code Review)
-
Sumeet R Pawnikar (Code Review)
-
Tim Wawrzynczak (Code Review)