Sumeet R Pawnikar has uploaded this change for review.

View Change

mb/google/dedede/variants/drawcia: add DTT support

Add DTT support on jasperlake based drawcia system.
Add information on sensors, power limits and tcc_offset
for DTT based thermal control.

BRANCH=None
BUG=None
TEST=Built for dedede system

Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/1
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 78fec88..d355201 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -39,7 +39,45 @@
},
}"

+ register "tcc_offset" = "20" # TCC of 80C
+
device domain 0 on
+ device pci 04.0 on
+ chip drivers/intel/dptf
+
+ register "options.tsr[0].desc" = ""Memory""
+ register "options.tsr[1].desc" = ""Ambient""
+ register "options.tsr[2].desc" = ""5V""
+ register "options.tsr[3].desc" = ""Charger""
+
+ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 10000)"
+ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 60000)"
+ register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 45, 15000)"
+ register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 50, 15000)"
+ register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 50, 15000)"
+
+ register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
+ register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN)"
+ register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN)"
+ register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN)"
+ register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)"
+
+ register "controls.power_limits.pl1" = "{
+ .min_power = 3000,
+ .max_power = 6000,
+ .time_window_min = 1 * MSECS_PER_SEC,
+ .time_window_max = 1 * MSECS_PER_SEC,
+ .granularity = 200,}"
+ register "controls.power_limits.pl2" = "{
+ .min_power = 6000,
+ .max_power = 20000,
+ .time_window_min = 1 * MSECS_PER_SEC,
+ .time_window_max = 1 * MSECS_PER_SEC,
+ .granularity = 1000,}"
+
+ device generic 0 on end
+ end
+ end # SA Thermal device
device pci 14.0 on
chip drivers/usb/acpi
device usb 0.0 on

To view, visit change 44148. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Gerrit-Change-Number: 44148
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Gerrit-MessageType: newchange