Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44171 )
Change subject: xeon_sp/cpx: Set HWP base feature ......................................................................
xeon_sp/cpx: Set HWP base feature
Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040
Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44171/1
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 1df5c13..cf903b8 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -64,6 +64,18 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic();
+ /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT;
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44171 )
Change subject: xeon_sp/cpx: Enable HWP Intel Speed Shift ......................................................................
Set Ready For Review
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44171 )
Change subject: xeon_sp/cpx: Enable HWP Intel Speed Shift ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44171 )
Change subject: xeon_sp/cpx: Enable HWP Intel Speed Shift ......................................................................
xeon_sp/cpx: Enable HWP Intel Speed Shift
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR
Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040
Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 12 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 1df5c13..cf903b8 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -64,6 +64,18 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic();
+ /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT;
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Angel Pons (Code Review) -
Johnny Lin (Code Review)