Patch set updated for coreboot: vendorcode/intel/skykabylake: Update CpuConfigFspData.h file

[Aamir Bohra]

Aamir Bohra ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285

-gerrit

commit 9afac37cfd6616c6d0605cebf33fd3082f802f53
Author: Barnali Sarkar 
Date:   Fri Feb 3 13:28:46 2017 +0530

vendorcode/intel/skykabylake: Update CpuConfigFspData.h file

The FSP UPD offsets and the corresponding structure size do not match,
    CpuConfigData.h needs an update to align the same. Hence update the
    header file based on FSP version 1.4.0.

BUG=chrome-os-partner:61548
    BRANCH=none
    TEST=Build and booted KBLRVP and verify that all UPDs are in sync in
    both coreboot and FSP.

Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
    Signed-off-by: Barnali Sarkar 
---
 .../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h       | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
index 8fd41e0..c8cdc5f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
@@ -62,9 +62,9 @@ typedef union {
     UINT32 TxtEnable           : 1;
     UINT32 SkipMpInit          : 1;                 ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
     UINT32 RsvdBits            : 15;                ///< Reserved for future use
-    EFI_PHYSICAL_ADDRESS MicrocodePatchAddress;     ///< Pointer to microcode patch that is suitable for this processor.
+    UINT32 Reserved;
   } Bits;
-  UINT32 Uint32[3];
+  UINT32 Uint32[2];
 } CPU_CONFIG_FSP_DATA;
 #pragma pack (pop)