Change in ...coreboot[master]: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
Hello Daniel Kurtz,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30922
to review the following change.
Change subject: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage ......................................................................
mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
The general rule is to configure GPIOs used by coreboot in bootblock (using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to properly set up debounce, however, it is no longer possible to change bootblock, so we also configure it in RAM stage to make the new debounce configuration take affect.
Signed-off-by: Daniel Kurtz djkurtz@chromium.org
BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30922/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c..399c78c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -117,6 +117,9 @@ /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP),
+ /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30922 )
Change subject: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage ......................................................................
Patch Set 1: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30922 )
Change subject: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage ......................................................................
mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
The general rule is to configure GPIOs used by coreboot in bootblock (using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to properly set up debounce, however, it is no longer possible to change bootblock, so we also configure it in RAM stage to make the new debounce configuration take affect.
Signed-off-by: Daniel Kurtz djkurtz@chromium.org
BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 Reviewed-on: https://review.coreboot.org/c/30922 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c..399c78c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -117,6 +117,9 @@ /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP),
+ /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
-
Daniel Kurtz (Code Review) -
Martin Roth (Code Review)