Change in coreboot[master]: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35994 )

Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
......................................................................

cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.

Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.

Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994
Reviewed-by: Angel Pons 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_6fx/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 037234a..16bc03b 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -13,3 +13,4 @@
    select SUPPORT_CPU_UCODE_IN_CBFS
    select CPU_INTEL_COMMON
    select CPU_INTEL_COMMON_TIMEBASE
+	select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 32f6e8c..e6c8256 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -14,3 +14,4 @@
    select SUPPORT_CPU_UCODE_IN_CBFS
    select CPU_INTEL_COMMON
    select CPU_INTEL_COMMON_TIMEBASE
+	select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK